GND ICS8305I-02 Low Skew, 1-to-4 Multiplexed Differential/ LVCMOS-to-LVCMOS Fanout Buffer DATA SHEET PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2016 General Description Features The ICS8305I-02 is a low skew, 1-to-4, Differential/ Four LVCMOS/LVTTL outputs, (two banks of two LVCMOS outputs) LVCMOS-to-LVCMOS/LVTTL Fanout Buffer. The ICS8305I-02 has selectable clock inputs that accept either differential or single-ended Selectable differential CLK, nCLK pair or LVCMOS CLK input input levels. The clock enable is internally synchronized to eliminate CLK, nCLK pair can accept the following differential input levels: runt pulses on the outputs during asynchronous assertion/ LVPECL, LVDS, LVHSTL, HCSL deassertion of the clock enable pin. Outputs are forced LOW when LVCMOS CLK supports the following input types: LVCMOS, the clock is disabled. A separate output enable pin controls whether LVTTL the outputs are in the active or high impedance state. Maximum output frequency: 250MHz Guaranteed output and part-to-part skew characteristics make the Output skew: 100ps (maximum) ICS8305I-02 ideal for those applications demanding well defined Power supply modes: performance and repeatability. Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 3.3V/1.5V -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging For functional replacement device use 8305 Block Diagram Pin Assignment QA0 OEA 1 16 Pullup OEA 2 15 VDDO A OEB V DD 3 14 QA1 Pullup CLK EN 4 13 GND CLK EN D CLK 5 12 QB0 Q nCLK 6 11 VDDO B LE Pulldown CLK SEL 7 10 QB1 LVCMOS CLK 00 LVCMOS CLK 8 9 QA0 Pulldown CLK 1 1 Pullup ICS8305I-02 nCLK QA1 16-Lead TSSOP Pullup CLK SEL 4.4mm x 5.0mm x 0.92mm package body G Package QB0 Top View QB1 Pullup OEB ICS8305AGI-02 REVISION A May 6, 2016 1 2016 Integrated Device Technology, Inc.ICS8305I-02 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description Output enable for Bank A outputs. When LOW, QAx outputs are in HIGH 1 OEA Input Pullup impedance state. When HIGH, QAx outputs are active. LVCMOS / LVTTL interface levels. Output enable for Bank B outputs. When LOW, QBx outputs are in HIGH 2 OEB Input Pullup impedance state. When HIGH, QBx outputs are active. LVCMOS / LVTTL interface levels. 3V Power Positive supply pins. DD Synchronizing clock enable. When LOW, the output clocks are disabled. When 4 CLK EN Input Pullup HIGH, output clocks are enabled. LVCMOS / LVTTL interface levels. 5 CLK Input Pulldown Non-inverting differential clock input. 6 nCLK Input Pullup Inverting differential clock input. Clock select input. When HIGH, selects CLK, nCLK inputs. 7 CLK SEL Input Pullup When LOW, selects LVCMOS CLK input. LVCMOS / LVTTL interface levels. 8 LVCMOS CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 9, 13 GND Power Power supply ground. 10, 12 QB1, QB0 Output Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels. 11 V Power Output supply pin for Bank B outputs. DDO B 14, 16 QA1, QA0 Output Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels. 15 V Power Output supply pin for Bank A outputs. DDO A NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN Input Pullup Resistor 51 k R PULLUP R Input Pulldown Resistor 51 k PULLDOWN Power Dissipation Capacitance C 13 pF PD (per output) V = V = 3.3V 9 DDO A DDO B V = V = 2.5V 11 DDO A DDO B R Output Impedance OUT V = V = 1.8V 15 DDO A DDO B V = V = 1.5V 20 DDO A DDO B ICS8305AGI-02 REVISION A May 6, 2016 2 2016 Integrated Device Technology, Inc.