LOW SKEW, 1-TO-16, LVCMOS/LVTTL ICS8316 FANOUT BUFFER W/1.2V LVCMOS OUTPUTS GENERAL DESCRIPTION FEATURES The ICS8316 is a low skew, 1-to-16 LVCMOS/LVTTL Sixteen 1.2V LVCMOS / LVTTL outputs ICS Fanout Buffer with 1.2V LVCMOS Outputs and a LVCMOS / LVTTL clock input HiPerClockS member of the HiPerClockS family of High Perfor- mance Clock Solutions from IDT. The ICS8316 single Maximum output frequency: 150MHz ended clock input accepts LVCMOS or LVTTL input Output skew: 380ps (maximum) levels. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. Propagation delay: 4.6ns (maximum) Guaranteed output and part-to-part skew characteristics 3.3V core/1.2V output operating supply mode along with the 1.2V output makes the ICS8316 ideal for high per- 0C to 70C ambient operating temperature formance, single ended applications that also require a limited output voltage. Industrial temperature information available upon request Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT CLK 32 31 30 29 28 27 26 25 4 QA0:QA3 VDDO 1 24 VDDO OEA QA0 2 QC0 23 4 QB0:QB3 QA1 3 QC1 22 OEB QA2 4 QC2 21 ICS8316 4 QC0:QC3 QA3 5 QC3 20 GND 6 19 GND OEC OEA 7 18 OEC 4 QD0:QD3 CLK GND 8 17 OED 9 10 11 12 13 14 15 16 32-Lead VFQFN 5mm x 5mm x 0.925 package body K Package Top View IDT / ICS 1-TO-16, 1.2V LVCMOS FANOUT BUFFER 1 ICS8316AK REV. B FEBRUARY 29, 2008 VDD GND OEB OED GND GND QB3 QD3 QB2 QD2 QB1 QD1 QB0 QD0 VDDO VDDOICS8316 LOW SKEW, 1-TO-16, LVCMOS/LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS TABLE 1. PIN DESCRIPTIONS Neumber Neam Tnyp Descriptio 1V, 16, 24, 25 P.ower Output supply pins DDO 23, 3, 4, 5QtA0, QA1, QA2, QA Outpu Bank A clock outputs. LVCMOS / LVTTL interface levels. 6, 11, 17, GrNDP.owe Power supply ground 19, 30, 32 Bank A output enable pin. Controls enabling and disabling 7AOtE Ipnpu Pullu of QA0:QA3 outputs. LVCMOS / LVTTL interface levels. 8KCtL InnpuP.ulldow Clock input. LVCMOS / LVTTL interface levels 9VP.ower Power supply pin DD Bank B output enable pin. Controls enabling and disabling 1B0 OtE Ipnpu Pullu of QB0:QB3 outputs. LVCMOS / LVTTL interface levels. 102, 13, 14, 15QtB3, QB2, QB1, QB Outpu Bank B clock outputs. LVCMOS / LVTTL interface levels. Bank C output enable pin. Controls enabling and disabling 1C8 OtE Ipnpu Pullu of QC0:QC3 outputs. LVCMOS / LVTTL interface levels. 200, 21, 22, 23QtC3, QC2, QC1, QC Outpu Bank C clock outputs. LVCMOS / LVTTL interface levels. 236, 27, 28, 29QtD0, QD1, QD2, QD Outpu Bank D clock outputs. LVCMOS / LVTTL interface levels. Bank D output enable pin. Controls enabling and disabling 3D1 OtE Ipnpu Pullu of QD0:QD3 outputs. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS SrymbolPsaramete Tmest Condition MlinimuTmypicaMsaximu Unit C Input Capacitance 4Fp IN Power Dissipation Capacitance C V=51.26V 1Fp PD DDO (per output) R Input Pullup Resistor 5k1 PULLUP R Input Pulldown Resistor 5k1 PULLDOWN ROVutput Impedance =81.2 5% 113 2 OUT DDO TABLE 3A. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE Csontrol Inputs Output O3E A:D Qx0:Qx 0ZHi- 1eActiv TABLE 3B. CLOCK INPUT FUNCTION TABLE Isnputs Output OKE A:D C3L Qx0:Qx 10 LOW 11 HIGH IDT / ICS 1-TO-16, 1.2V LVCMOS FANOUT BUFFER 2 ICS8316AK REV. B FEBRUARY 29, 2008