HCSL/ LVCMOS Clock Generator 8413S12B General Description Features The 8413S12B is a PLL-based clock generator. This high Ten selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz clocks for PCI Express, sRIO and GbE, HCSL interface levels performance device is optimized to generate the processor core reference clock, the PCI-Express, sRIO, XAUI, SerDes reference One single-ended QG LVCMOS/LVTTL clock output at 125MHz clocks and the clocks for both the Gigabit Ethernet MAC and PHY. One single-ended QF LVCMOS/LVTTL clock output at 50MHz, The clock generator offers ultra low-jitter, low-skew clock outputs. 15 output impedance The output frequencies are generated from a 25MHz external input Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz, source or an external 25MHz parallel resonant crystal. The industrial 15 output impedance temperature range of the 8413S12B supports telecommunication, networking, and storage requirements. Selectable external crystal or differential (single-ended) input source Crystal oscillator interface designed for 25MHz, parallel resonant Applications crystal CPE Gateway Design Differential CLK, nCLK input pair that can accept: LVPECL, LVDS, Home Media Servers LVHSTL, HCSL input levels 802.11n AP or Gateway Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels Soho Secure Gateway Supply Modes, (125MHz QG output and 25MHz QREFx outputs): Soho SME Gateway Wireless Soho and SME VPN Solutions Core / Output 3.3V / 3.3V Wired and Wireless Network Security 3.3V / 2.5V Web Servers and Exchange Servers Supply Modes, (HCSL outputs, and 50MHz QF output): Core / Output 3.3V / 3.3V Pin Assignment -40C to 85C ambient operating temperature Available in Lead-free (RoHS 6) package 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 GND 1 54 nc FSEL A0 2 53 V DD FSEL A1 3 52 IREF 51 OE D FSEL B0 4 FSEL B1 5 50 nQD1 FSEL C0 6 49 QD1 FSEL C1 7 48 nQD0 47 QD0 FSEL D0 8 FSEL D1 9 46 V DDO D 6 FSEL E0 10 45 V DDO C V 11 44 nQC1 DDA 12 43 QC1 FSEL E1 nc 13 42 nQC0 XTAL IN 14 41 QC0 XTAL OUT 15 40 OE C 16 39 V nc DD REF SEL 17 38 GND GND 18 37 nc 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SLQ PP PP /4)3 3DFNDJH 2016 Integrated Device Technology, Inc. 1 Revision E, August 18, 2016 nc nc V V DD DDO QREF QREF1 PLL SEL CLK QREF0 nCLK OE REF OE A OE G QG V DDO A QA0 V DDO G nQA0 QF QA1 V DDO F nMR nQA1 OE B OE E QB0 nQE1 nQB0 QE1 nQE0 QB1 nQB1 QE0 V V DDO B DDO E nc nc8413S12B Datasheet. Block Diagram Pullup nMR OE A QA0, 00 = 100MHz nQA0 2 Pulldown 01 = 125MHz FSEL A 0:1 10 = 156.25MHz QA1, 11 = 312.5MHz 2 Pulldown nQA1 FSEL B 0:1 Clock OE B 2 Output Pulldown QB0, FSEL C 0:1 00 = 100MHz Control nQB0 01 = 125MHz Logic 2 Pulldown FSEL D 0:1 10 = 156.25MHz QB1, 11 = 312.5MHz 2 nQB1 Pulldown FSEL E 0:1 OE C QC0, 00 = 100MHz nQC0 01 = 125MHz Pullup PLL SEL 10 = 156.25MHz QC1, 11 = 312.5MHz nQC1 Pullup REF SEL OE D QD0, 00 = 100MHz nQD0 01 = 125MHz Pulldown CLK, 10 = 156.25MHz 0 QD1, nCLK 11 = 312.5MHz 0 nQD1 Pullup/ VCO 1 OE E Pulldown 1 QE0, 00 = 100MHz XTAL IN nQE0 01 = 125MHz OSC 10 = 156.25MHz QE1, XTAL OUT 11 = 312.5MHz nQE1 IREF 50MHz QF OE G 125MHz QG OE REF QREF0 QREF1 NOTE: OE A:G and OE REF pins have pullup resistors. 2016 Integrated Device Technology, Inc 2 Revision E, August 18, 2016