VCCO VCCO CLK1 VEE nCLK1 VCC SEL8 SEL11 SEL7 SEL10 SEL6 SEL9 SEL0 SEL3 SEL1 SEL4 SEL2 SEL5 CLK0 VCC nCLK0 VEE VCCO VCCO 12 Bit, 2-to-1, 3.3V, 2.5V LVPECL Clock Buffer 85352 Datasheet General Description Features The 85352 is a 12 bit, 2-to-1 LVPECL Clock Buffer. Individual input Twelve, 2-to-1 multiplexers with LVPECL outputs select controls support independent multiplexer operation from a Selectable differential CLKx, nCLKx input pairs common clock input source. Clock inputs accept most standard CLK, nCLK pair can accept the following differential input differential levels. levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL The 85352 is characterized at full 3.3V or mixed 3.3V core/2.5V Maximum output frequency: 700MHz output operating supply modes. Individual select control for each multiplexer Select inputs accept LVCMOS / LVTTL levels Propagation delay: 2ns (maximum) Additive Phase Jitter, RMS: 0.21ps (typical), 3.3V Full 3.3V or mixed 3.3V core/2.5V output supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment 12 Pulldown SEL0:SEL11 Pulldown CLK0 Pullup/Pulldown 0 nCLK0 Q0 nQ0 48 47 46 45 44 43 42 41 40 39 38 37 Pulldown CLK1 Q0 1 36 Q6 1 Pullup/Pulldown nCLK1 nQ0 2 35 nQ6 Q1 3 34 Q7 nQ1 4 33 nQ7 Q2 5 32 Q8 nQ2 6 31 nQ8 85352 Q3 7 30 Q9 nQ3 8 29 nQ9 Q4 9 28 Q10 nQ4 10 27 nQ10 Q5 11 26 Q11 nQ5 12 25 nQ11 0 13 14 15 16 17 18 19 20 21 22 23 24 Q11 nQ11 1 85352 48-Lead TQFP, E-Pad 7mm x 7mm x 1.0mm package body Y Package Top View 2015 Integrated Device Technology, Inc. 1 Revision D, December 1, 201585352 Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1, 2 Q0, nQ0 3, 4 Q1, nQ1 5, 6 Q2, nQ2 7, 8 Q3, nQ3 9, 10 Q4, nQ4 11, 12 Q5, nQ5 Output Differential output pairs. LVPECL interface levels. 25, 26 nQ11, Q11 27, 28 nQ10, Q10 29, 30 nQ9, Q9 31, 32 nQ8, Q8 33, 34 nQ7, Q7 35, 36 nQ6, Q6 13, 24, 37, 48 V Power Output power supply pins. CCO 14, 23 V Power Negative power supply pins. EE 15, 22 V Power Positive power supply pins. CC 16, 17, SEL5, SEL4, 18, 19, SEL3, SEL9, 20, 21, SEL10, SEL11, Input Pulldown Clock select inputs. LVCMOS / LVTTL interface levels. See Table 3. 40, 41, SEL8, SEL7, 42, 43, SEL6, SEL0, 44, 45 SEL1, SEL2 38 CLK1 Input Pulldown Non-inverting differential clock input. Pullup/ 39 nCLK1 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 46 CLK0 Input Pulldown Non-inverting differential clock input. Pullup/ 47 nCLK0 Input Inverting differential clock input. V /2 default when left floating CC Pulldown NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN Function Table Table 3. Control Input Function Table SELx Selected Clock inputs 0 CLK0, nCLK0 1 CLK1, nCLK1 2015 Integrated Device Technology, Inc. 2 Revision C, December 1, 2015