Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V ICS8535I-01 LVPECL Fanout Buffer GENERAL DESCRIPTION FEATURES The ICS8535I-01 is a low skew, high performance 1-to-4 Four differential 3.3V LVPECL outputs LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The Selectable CLK0 or CLK1 inputs for redundant ICS8535I-01 has two single ended clock inputs. the single and multiple frequency fanout applications ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The clock CLK0 or CLK1 can accept the following input levels: enable is internally synchronized to eliminate runt clock LVCMOS or LVTTL pulses on the output during asynchronous assertion/ Maximum output frequency: 266MHz deassertion of the clock enable pin. Translates LVCMOS and LVTTL levels to Guaranteed output and part-to-part skew characteristics 3.3V LVPECL levels make the ICS8535I-01 ideal for those applications demand- ing well defined performance and repeatability. Output skew: 30ps (maximum) Part-to-part skew: 250ps (maximum) Propagation delay: 1.9ns (maximum) Jitter, RMS: < 0.09ps (typical) 3.3V operating supply -40C to 85C ambient operating temperature Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT VEE 1 20 Q0 D CLK EN CLK EN 2 19 nQ0 Q CLK SEL 3 18 VCC LE CLK0 4 17 Q1 CLK0 0 5 16 nc nQ1 Q0 CLK1 6 15 Q2 nQ0 CLK1 1 nc 7 14 nQ2 13 Q1 nc 8 VCC nQ1 nc 9 12 Q3 CLK SEL 10 11 VCC nQ3 Q2 nQ2 ICS8535I-01 Q3 20-Lead TSSOP nQ3 4.4mm x 6.5mm x 0.92mm body package G Package Top View 8535AGI-01 www.idt.com REV. F MAY 28, 2013 1Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V ICS8535I-01 LVPECL Fanout Buffer TABLE 1. PIN DESCRIPTIONS NeumberNeam Tnyp Descriptio 1VP.ower Negative supply pin EE Synchronizing clock enable. When HIGH, clock outputs follow clock input. 2NCtLK EIpnpu Pullu When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1 input. 3LCtLK SEInnpu Pulldow When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. 40CtLKInnpuP.ulldow LVCMOS / LVTTL clock input 61CtLKInnpuP.ulldow LVCMOS / LVTTL clock input 5c, 7, 8, 9 ndU.nuse No connect 1V0, 13, 18P.ower Positive supply pins CC 131, 12ntQ3, QO.utpu Differential output pair. LVPECL interface levels 124, 15ntQ2, QO.utpu Differential output pair. LVPECL interface levels 116, 17ntQ1, QO.utpu Differential output pair. LVPECL interface levels 109, 20ntQ0, QO.utpu Differential output pair. LVPECL interface levels NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS SrymbolPsaramete Tmest Condition MlinimuTmypicaMsaximu Unit C Input Capacitance 4Fp IN R Input Pullup Resistor 5k1 PULLUP R Input Pulldown Resistor 5k1 PULLDOWN 8535AGI-01 www.idt.com REV. F MAY 28, 2013 2