GND nPCLK4 8:1 Differential-to-LVDS Clock Multiplexer ICS854S058I DATASHEET General Description Features The ICS854S058I is an 8:1 Differential-to-LVDS Clock Multiplexer High speed 8:1 differential multiplexer which can operate up to 2.5GHz. The ICS854S058I has 8 One differential LVDS output pair selectable differential clock inputs. The PCLK, nPCLK input pairs Eight selectable differential PCLK, nPCLK input pairs can accept LVPECL, LVDS, SSTL or CML levels. The fully PCLKx, nPCLKx pairs can accept the following differential differential architecture and low propagation delay make it ideal for input levels: LVPECL, LVDS, SSTL, CML use in clock distribution circuits. The select pins have internal Maximum output frequency: 2.5GHz pulldown resistors. The SEL2 pin is the most significant bit and the binary number applied to the select pins will select the same Translates any single ended input signal to LVDS levels with numbered data input (i.e., 000 selects PCLK0, nPCLK0). resistor bias on nPCLKx input Additive phase jitter, RMS: 0.065ps (typical) Part-to-part skew: 300ps (maximum) Propagation delay: 600ps (maximum) Supply voltage range: 3.135V to 3.465V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) packaging Block Diagram Pin Assignment PCLK0 1 24 PCLK7 nPCLK0 2 23 nPCLK7 Pulldown PCLK0 Pullup/Pulldown 0 0 0 PCLK1 3 22 PCLK6 nPCLK0 (default) nPCLK1 4 21 nPCLK6 Pulldown PCLK1 V 5 20 VDD DD Pullup/Pulldown 0 0 1 nPCLK1 SEL0 6 19 Q SEL1 7 18 nQ Pulldown PCLK2 SEL2 8 17 Pullup/Pulldown 0 1 0 nPCLK2 PCLK2 9 16 PCLK5 nPCLK2 10 15 nPCLK5 Pulldown PCLK3 PCLK3 11 14 PCLK4 Pullup/Pulldown 0 1 1 nPCLK3 nPCLK3 12 13 Q Pulldown PCLK4 nQ ICS854S058I Pullup/Pulldown 1 0 0 nPCLK4 24-Lead TSSOP, 173-MIL Pulldown PCLK5 7.8mm x 4.4mm x 0.925mm package body 1 0 1 Pullup/Pulldown nPCLK5 G Package Pulldown PCLK6 Top View Pullup/Pulldown 1 1 0 nPCLK6 Pulldown PCLK7 Pullup/Pulldown 1 1 1 nPCLK7 Pulldown SEL2 Pulldown SEL1 Pulldown SEL0 ICS854S058AGI REVISION A OCTOBER 29, 2012 1 2012 Integrated Device Technology, Inc.ICS854S058I Datasheet 8:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER Table 1. Pin Descriptions Number Name Type Description 1 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 2 nPCLK0 Input Inverting differential LVPECL clock input. V /2 default when left floating. DD Pulldown 3 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 4 nPCLK1 Input Inverting differential LVPECL clock input. V /2 default when left floating. DD Pulldown 5, 20 V Power Positive supply pins. DD SEL0, 6, 7, 8 SEL1, Input Pulldown Clock select input pins. LVCMOS/LVTTL interface levels. SEL2 9 PCLK2 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 10 nPCLK2 Input Inverting differential LVPECL clock input. V /2 default when left floating. DD Pulldown 11 PCLK3 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 12 nPCLK3 Input Inverting differential LVPECL clock input. V /2 default when left floating. DD Pulldown Pullup/ 13 nPCLK4 Input Inverting differential LVPECL clock input. V /2 default when left floating. DD Pulldown 14 PCLK4 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 15 nPCLK5 Input Inverting differential LVPECL clock input. V /2 default when left floating. DD Pulldown 16 PCLK5 Input Pulldown Non-inverting differential LVPECL clock input. 17 GND Power Power supply ground. 18, 19 nQ, Q Output Differential output pair. LVDS interface levels. Pullup/ 21 nPCLK6 Input Inverting differential LVPECL clock input. V /2 default when left floating. DD Pulldown 22 PCLK6 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 23 nPCLK7 Input Inverting differential LVPECL clock input. V /2 default when left floating. DD Pulldown 24 PCLK7 Input Pulldown Non-inverting differential LVPECL clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 2 pF C IN R Pulldown Resistor 75 k PULLDOWN R /2 RPullup/Pulldown Resistor 50 k VDD ICS854S058AGI REVISION A OCTOBER 29, 2012 2 2012 Integrated Device Technology, Inc.