15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ 86004I LVTTL Zero Delay Clock Buffer DATA SHEET GENERAL DESCRIPTION FEATURES Four LVCMOS/LVTTL outputs, 7 typical output impedance The 86004I is a high performance 1:4 LVCMOS/LVTTL Clock Buffer. The 86004I has a fully integrated PLL and can be con gured as Single LVCMOS/LVTTL clock input zero delay buffer and has an input and output frequency range of CLK accepts the following input levels: LVCMOS or LVTTL 15.625MHz to 62.5MHz. The VCO operates at a frequency range of 250MHz to 500MHz. The external feedback allows the device to Output frequency range: 15.625MHz to 62.5MHz achieve zero delay between the input clock and the output clocks. Input frequency range: 15.625MHz to 62.5MHz The PLL SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed VCO range: 250MHz to 500MHz around the PLL and into the internal output divider. External feedback for zero delay clock regeneration with con gurable frequencies Fully integrated PLL Cycle-to-cycle jitter: 75ps (maximum) Output skew: 65ps (maximum) Full 3.3V or 2.5V, or 3.3V core/2.5V output operating supply -40C to 85 ambient operating temperature Available in lead-free RoHS compliant package BLOCK DIAGRAM PIN ASSIGNMENT 86004I 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View 86004I REVISION A 7/10/15 1 2015 Integrated Device Technology, Inc.86004I DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 3, Q1, Q0, Output Clock outputs. 7 typical output impedance. LVCMOS/LVTTL interface levels. 13, 15 Q3, Q2 2, 7, 14 GND Power Power supply ground. Frequency range select input. See Table 3A and 3B. 4 F SEL Input Pulldown LVCMOS/LVTTL interface levels. 5V Power Core supply pin. DD 6 CLK Input Pulldown LVCMOS/LVTTL clock input. 8V Power Analog supply pin. DDA Selects between the PLL and reference clock as input to the dividers. 9 PLL SEL Input Pullup When LOW, selects the reference clock (PLL Bypass). When HIGH, selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels. Feedback input to phase detector for regenerating clocks with zero delay. 10 FB IN Input Pulldown Connect to one of the outputs. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset 11 MR Input Pulldown causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 12, 16 V Power Output supply pins. DDO NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V , V , V = 3.465V 23 pF Power Dissipation Capacitance DD DDA DDO C PD (per output) V , V , V = 2.625V 17 pF DD DDA DDO R Output Impedance 3.3V 5% 5 7 12 OUT TABLE 3A. CONTROL INPUT FUNCTION TABLE, PLL SEL = 1 TABLE 3B. CONTROL INPUT FUNCTION TABLE, PLL SEL = 0 Input/Output Input Input Output Frequency Range (MHz) F SEL F SEL Minimum Maximum 0 Ref 8 0 31.25 62.5 1 Ref 16 1 15.625 31.25 15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ 2 REVISION A 7/10/15 LVTTL Zero Delay Clock Buffer