LVPECL Frequency-Programmable VCXO IDT8N3SV75 DATASHEET General Description Features The IDT8N3SV75 is a LVPECL Frequency-ProgrammableVCXO Fourth generation FemtoClock NG technology withveryflexiblefrequencyandpull-rangeprogrammingcapabilities. Programmable clock output frequency from 15.476MHz to The device uses IDTs fourth generation FemtoClock NG 866.67MHz and from 975MHz to 1,300MHz technology for an optimum of high clock frequency and low phase Frequency programming resolution is 218Hz and better noise performance.The device accepts 2.5V or 3.3V supply and is packagedinasmall,lead-free(RoHS6)6-leadceramic5mmx7mm Factory-programmableVCXO pull range and control voltage polarity x 1.55mm package. Absolute pull range (APR) programmable from typical 4.5 to The device can be factory-programmed to any frequency in the 754.5ppm range of 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz to the very high degree of frequency precision of 218Hz or better. One 2.5V/3.3V LVPECL clock output The extended temperature range supports wireless infrastructure, Output enable control input, LVCMOS/LVTTL compatible telecommunication and networking end equipment requirements. RMS phase jitter 156.25MHz (12kHz - 20MHz): 0.5ps (typical), 2.5V or 3.3V supply voltage -40C to 85C ambient operating temperature Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm package Block Diagram Pin Assignment VC 1 6 V CC OE 2 5 nQ PFD FemtoClock NG Q P VEE 3 4 Q OSC & N VCO nQ LPF 1950-2600MHz IDT8N3SV75 114.285MHz 6-lead ceramic 5mm x 7mm x 1.55mm package body 2 MINT, MFRAC CD Package TopView A/D VC 7 25 7 Configuration Register (ROM) (Frequency, Pull-range, Polarity) Pullup OE IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 1 2013 Integrated Device Technology, Inc.IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Pin Description and Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 VC Input VCXO Control Voltage input. Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface 2 OE Input Pullup levels. 3V Power Negative power supply. EE 4, 5 Output Differential clock output. LVPECL interface levels. Q, nQ 6 Power Positive power supply. V CC NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units OE 5.5 pF Input Capacitance C IN VC 10 pF Input Pullup Resistor 50 k R PULLUP Function Tables Table 3A. OE Configuration Input OE Output Enable 0 Outputs Q, nQ are in high-impedance state. 1 (default) Outputs are enabled. Table 3B. Output Frequency Range 15.476MHz to 866.67MHz 975MHz to 1,300MHz NOTE: Supported output frequency range.The output frequency can be programmed to any frequency in this range and to a precision of better. 218Hz or IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 2 2013 Integrated Device Technology, Inc.