Dual 1:4, LVDS Output Fanout Buffer 8SLVD2104 DATA SHEET Features General Description Two 1:4, low skew, low additive jitter LVDS fanout buffers The 8SLVD2104 is a high-performance differential dual 1:4 LVDS fanout buffer. The device is designed for the fanout of high-frequency, Two differential clock inputs very low additive phase-noise clock and data signals. The Differential pairs can accept the following differential input 8SLVD2104 is characterized to operate from a 2.5V power supply. levels: LVDS and LVPECL Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD2104 ideal for those clock distribution applications Maximum input clock frequency: 2GHz demanding well-defined performance and repeatability. Two Output bank skew: 35ps, (maximum) independent buffers with four low skew outputs each are available. The integrated bias voltage generators enables easy interfacing of Propagation delay: 300ps, (maximum) single-ended signals to the device inputs. The device is optimized for Low additive RMS phase jitter, 156.25MHz (10kHz - 20MHz): low power consumption and low additive phase noise. 105fs, (maximum) 2.5V supply voltage Lead-free (RoHS 6) 28-Lead VFQFN package -40C to 85C ambient operating temperature Block Diagram Pin Assignment 28 27 26 25 24 23 22 1 GND 21 nQA3 2 QB3 20 QA3 3 nQB3 19 nQA2 8SLVD2104 EN 4 18 QA2 PCLKB 5 17 nQA1 nPCLKB 6 QA1 16 7 VREFB 15 VDD 8 9 10 11 12 13 14 28-Lead, 5mm x 5mm VFQFN 8SLVD2104 REVISION 1 08/03/15 1 2015 Integrated Device Technology, Inc. VDD VDD PCLKA nQB2 nPCLKA QB2 VREFA nQB1 QB1 QA0 nQA0 nQB0 QB0 GND8SLVD2104 DATA SHEET Pin Description and Pin Characteristic Tables 1 Table 1. Pin Descriptions Number Name Type Description 1 GND Power Power supply ground. 2 QB3 Output Differential output pair B3. LVDS interface levels. 3 nQB3 Output Pullup/ 4 EN Input Output enable pin. V /2 default when left floating. DD Pulldown 5 PCLKB Input Pulldown Non-inverting differential clock/data input. Pullup/ 6 nPCLKB Input Inverting differential clock/data input. V /2 default when left floating. DD Pulldown 7V Output Bias voltage reference for the PCLKB, nPCLKB input pair. REFB Power Power supply pin. 8V DD 9 PCLKA Input Pulldown Non-inverting differential clock/data input. Pullup/ 10 nPCLKA Input Inverting differential clock/data input. V /2 default when left floating. DD Pulldown 11 V Output Bias voltage reference for the PCLKA, nPCLKA input pair. REFA 12, QA0 Output Differential output pair A0. LVDS interface levels. 13 nQA0 Output 14 GND Power Power supply ground. 15 V Power Power supply pin. DD 16 QA1 Output Differential output pair A1. LVDS interface levels. 17 nQA1 Output 18, QA2 Output Differential output pair A2. LVDS interface levels. 19 nQA2 Output 20 QA3 Output Differential output pair A3. LVDS interface levels. 21 nQA3 Output 22 QB0 Output Differential output pair B0. LVDS interface levels. 23 nQB0 Output 24 QB1 Output Differential output pair B1. LVDS interface levels. 25 nQB1 Output 26 QB2 Output Differential output pair B2. LVDS interface levels. 27 nQB2 Output 28 V Power Power supply pin. DD ePAD Thermal pad. Connect to ground. NOTE 1: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. DUAL 1:4, LVDS OUTPUT FANOUT BUFFER 2 REVISION 1 08/03/15