Crystal or Differential to 8T39S04A Differential Clock Fanout Buffer Datasheet Description Features The 8T39S04A is a high-performance clock fanout buffer. The input Two differential reference clock input pairs clock can be selected from two differential inputs or one crystal input. Differential input pairs can accept the following input levels: The internal oscillator circuit is automatically disabled if the crystal LVPECL, LVDS, HCSL, HSTL and Single-ended input is not selected. The crystal pin can be driven by a single-ended Crystal Oscillator Interface clock. The selected signal is distributed to four differential outputs which can be configured as LVPECL, LVDS or HSCL outputs. In Crystal input frequency range: 10MHz to 40MHz addition, an LVCMOS output is provided. All outputs can be disabled Maximum Output Frequency into a high-impedance state. The device is designed for a signal LVPECL - 2GHz fanout of high-frequency, low phase-noise clock and data signal. The LVDS - 2GHz outputs are at a defined level when inputs are open or tied to ground. HCSL - 250MHz It is designed to operate from a 3.3V or 2.5V core power supply, and LVCMOS - 250MHz either a 3.3V or 2.5V output operating supply. Two banks, each has two differential output pairs that can be configured as LVPECL or LVDS or HCSL One single-ended reference output with synchronous enable to avoid clock glitch Output skew: 80ps (maximum), Bank A and Bank B at the same Block Diagram output level Part-to-part skew: 200ps (typical), design target PullDown Additive RMS phase jitter 156.25MHz, (12kHz - 20MHz): 34.7fs (typical), 3.3V/ 3.3V PullDown Supply voltage modes: V /V DD DDO 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Pin Assignment 24 23 22 21 20 19 18 17 nc 25 16 REF SEL1 REFOUT 26 nCLK1 15 nCLK0 27 CLK1 14 CLK0 28 V 13 DD REF SEL0 8T39S04A REFOUT 29 12 XTAL OUT 30 V 11 DDOREF XTAL IN 31 OE SE 10 V DD 32 SMODE1 9 SMODE0 1 23 4 5 67 8 32-pin,5mmx5mmVFQFNPackage 2019 Integrated Device Technology, Inc. 1 July 24, 2019 GND GND V V DDOA DDOB QA0 QB0 nQA0 nQB0 V V DDOA DDOB QA1 QB1 nQA1 nQB1 GND GND8T39S04A Datasheet Pin Description and Pin Characteristic Table Table 1. Pin Descriptions Number Name Type Description 1 GND Power Power supply ground. 2V Power Output supply pin for Bank QA outputs. DDOA 3 QA0 Output Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels. 4 nQA0 Output Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels. 5V Power Output supply pin for Bank QA outputs. DDOA 6 QA1 Output Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels. 7 nQA1 Output Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels. 8 GND Power Power supply ground. Output driver select for Bank A and Bank B outputs. See Table 3D for function. 9 SMODE0 Input Pulldown LVCMOS/LVTTL interface levels. 10 V Power Power supply pin. DD 11 XTAL IN Input Crystal oscillator interface. 12 XTAL OUT Output Crystal oscillator interface. Input clock selection. LVCMOS/LVTTL interface levels. 13 REF SEL0 Input Pulldown See Table 3A for function. Pullup/ 14 CLK0 Input Non-inverting differential clock. Internally biased to 0.33V DD. Pulldown Pullup/ 15 nCLK0 Input Inverting differential clock. Internal resistor bias to 0.4V . DD Pulldown Input clock selection. LVCMOS/LVTTL interface levels. 16 REF SEL1 Input Pulldown See Table 3A for function. 17 GND Power Power supply ground. 18 nQB1 Output Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels. 19 QB1 Output Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels. 20 V Power Output supply pin for Bank QB outputs. DDOB 21 nQB0 Output Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels. 22 QB0 Output Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels. 23 V Power Output supply pin for Bank QB outputs. DDOB 24 GND Power Power supply ground. 25 nc Unused No connect pin. Pullup/ 26 nCLK1 Input Inverting differential clock. Internal resistor bias to 0.4V . DD Pulldown Pullup/ 27 CLK1 Input Non-inverting differential clock. Internally biased to 0.33V DD. Pulldown 28 V Power Power supply pin. DD 29 REFOUT Output Single-ended reference clock output. LVCMOS/LVTTL interface levels. 30 V Power Output supply pin for REFOUT output. DDOREF 31 OE SE Input Pulldown Output enable. LVCMOS/LVTTL interface levels. See Table 3B. Output driver select for Bank A and Bank B outputs. See Table 3D for function. 32 SMODE1 Input Pulldown LVCMOS/LVTTL interface levels. 0 ePAD Power Connect ePAD to ground to ensure proper heat dissipation. NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 2019 Integrated Device Technology, Inc. 2 July 24, 2019