JESD204B Compliant Fanout Buffer 8V79S680 Datasheet and Divider Description Typical Applications JESD204B low phase noise clock and SYSREF signal The 8V79S680 is a fully integrated, clock and SYSREF signal distribution fanout buffer for JESD204B applications. It is designed as a high-performance clock and converter synchronization solution for Supports JESD204 subclass 0, 1 and 2 wireless base station radio equipment boards with JESD204B Clock distribution device for jitter-sensitive ADC and DAC subclass 0, 1, and 2 compliance. The main function of the device circuits is the distribution and fanout of high-frequency clocks and Wireless infrastructure low-frequency system reference signals generated by a Radar and imaging JESB204B clock generator such as the IDT 8V19N480, extending its fanout capabilities and providing additional phase-delay. Instrumentation and medical The 8V79S680 is optimized to deliver very low phase noise clocks Features and precise, phase-adjustable SYSREF synchronization signals as required in GSM, WCDMA, LTE, LTE-A radio board Supports high-speed, low phase noise converter clocks implementations. Low-skew outputs, low device-to-device skew Distribution, fanout, phase-delay of clock and SYSREF signals characteristics and fast output rise/fall times help the system Very low output noise floor: -158.8dBc/Hz noise floor design to achieve deterministic clock and SYSREF phase (245.76MHz) relationship across devices. Supports clock frequencies up to 3GHz, including clock output The device distributes the input clock (CLK) and JESD204B frequencies of 983.04MHz, 491.52MHz, 245.76MHz, and SYSREF signals (REF) to four fanout channels. In each channel, 122.88MHz both input clock and SYSREF signals are fanned-out to multiple 4 output channels with a total of 16 differential outputs, clock (QCLK) and SYSREF (QREF) outputs. Clock signals can be organized in: frequency-divided in each channel. Configurable phase-delay 8 dedicated clock outputs circuits are available for both clock and SYSREF signals. The propagation delays in all signal paths are fully deterministic to 8 outputs configurable as SYSREF outputs with individual support fixed phase relationships between clock and SYSREF phase delay stages, or configurable as additional clock signals within one device. Clock divider can be bypassed for outputs low-latency clock paths. The device facilitates synchronization Each channel contains: between frequency dividers within the device and across multiple Frequency dividers: 1, 2, 4, 6, 8, 12, 16 devices, removing phase ambiguity introduced in dividers Clock phase delay circuits between power and configuration cycles. Clock phase delay circuits Each channel supports clock frequencies up to 3GHz. In an Clock: delay unit is the clock period 256 steps alternative configuration, for instance JESD204B subclass 0 and SYSREF: Configurable precision phase delay circuits: 2, the SYSREF (QREF) outputs can be configured as regular 8 steps of 131ps, 262ps, 393ps, or 524ps clock outputs adding additional clock fanout to the device. Flexible differential outputs: All outputs are very flexible in amplitude configuration, output LVDS/LVPECL configurable signal termination and allow both DC and AC coupling. Outputs can be disabled and powered-down when not used. The SYSREF Amplitude configurable output pre-bias feature supports prevention of power-on glitches Power-down modes for unused outputs and enables AC-coupling of the system synchronization signals. Supports DC and AC coupling The device is configured through a 3-wire SPI serial interface. The QREF (SYSREF) output pre-bias feature to prevent glitches device is packaged in a lead-free (RoHS 6) 64-lead VFQFPN when turning output on or off package. The extended temperature range supports wireless Supply voltage: infrastructure, telecommunication and networking end equipment 3.3V core and signal I/O requirements. The device is a member of the high-performance 1.8V Digital control SPI I/O (3.3V-tolerant inputs) clock family from IDT. 64 VFQFPN package (9 9 0.85 mm) Ambient temperature range: -40C to +85C 2019 Integrated Device Technology, Inc 1 January 11, 20198V79S680 Datasheet Contents Description 1 Typical Applications . 1 Features 1 Contents 2 Block Diagram . 3 Pin Assignments 4 Pin Descriptions 5 Principles of Operation . 7 Overview . 7 Signal Flow . 7 Clock Channel Divider . 7 Phase Delay 8 Delay Calibration Block (DCB) 8 QCLK to SYSREF Phase Alignment . 10 Differential Outputs 11 Device Startup, Reset, and Synchronization . 13 Changing Frequency Dividers and Phase Delay Values . 13 SPI Interface . 14 Register Descriptions . 16 Channel and Clock Output Registers 19 QREF Output State Registers 21 SYSREF Control Registers . 24 General Control Registers 26 Electrical Characteristics 28 Absolute Maximum Ratings . 28 Pin Characteristics 28 DC Characteristics . 29 AC Characteristics 32 Additive Clock Phase Noise Characteristics . 35 Application Information 41 Termination for QCLK y, QREF r LVDS Outputs (STYLE = 0) 41 AC Termination for QCLK y, QREF r LVDS Outputs (STYLE = 0) . 41 Termination for QCLK y, QREF r LVPECL Outputs (STYLE = 1) 42 Package Exposed Pad Thermal Release Path . 42 Thermal Characteristics 43 Case Temperature Considerations 43 Example Calculation for Junction Temperature (TJ): TJ = TCB + YJB x PD 44 Package Outline Drawings . 44 Ordering Information . 44 Marking Diagram 44 Glossary . 45 Revision History . 45 2019 Integrated Device Technology, Inc 2 January 11, 2019