Integrated ICS9DB104 Circuit (Not recommended for new designs) Systems, Inc. Four Output Differential Buffer for PCI-Express Recommended Application: Pin Configuration DB400 Intel Yellow Cover part with PCI-Express support. VDD 1 28 VDDA SRC IN 2 27 GNDA Output Features: SRC IN 3 26 IREF 4 - 0.7V current-mode differential output pairs GND425GND Supports zero delay buffer mode and fanout mode 524VDD VDD Bandwidth programming available DIF 1623 DIF 6 722 DIF 1 DIF 6 Key Specifications: OE 1 8 21 OE 6 Outputs cycle-cycle jitter: < 50ps DIF 2920 DIF 5 Outputs skew: < 50ps DIF 2 10 19 DIF 5 +/- 300ppm frequency accuracy on output clocks 11 18 VDD VDD BYPASS /PLL 12 17 HIGH BW Features/Benefits: 13 16 SRC STOP SCLK Supports tight ppm accuracy clocks for Serial-ATA 14 15 PD SDATA Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread 28-pin SSOP & TSSOP Supports undriven differential output pair in PD and SRC STOP for power management. 0767E12/14/07 Not recommended for new designs ICS9DB104Integrated ICS9DB104 Circuit (Not recommended for new designs) Systems, Inc. Pin Description PIN PIN NAME PIN TYPE DESCRIPTION 1 VDD PWR Power supply, nominal 3.3V 2 SRC IN IN 0.7 V Differential SRC TRUE input 3 SRC IN IN 0.7 V Differential SRC COMPLEMENTARY input 4 GND PWR Ground pin. 5 VDD PWR Power supply, nominal 3.3V 6 DIF 1 OUT 0.7V differential true clock outputs 7 DIF 1 OUT 0.7V differential complement clock outputs Active high input for enabling outputs. 8 OE 1 IN 0 = tri-state outputs, 1= enable outputs 9 DIF 2 OUT 0.7V differential true clock outputs 10 DIF 2 OUT 0.7V differential complement clock outputs 11 VDD PWR Power supply, nominal 3.3V Input to select Bypass(fan-out) or PLL (ZDB) mode 12 BYPASS /PLL IN 0 = Bypass mode, 1= PLL mode 13 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 14 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. Asynchronous active low input pin used to power down the device. The 15 PD IN internal clocks are disabled and the VCO and the crystal are stopped. 16 SRC STOP IN Active low input to stop diff outputs. 3.3V input for selecting PLL Band Width 17 HIGH BW IN 0 = High, 1= Low 18 VDD PWR Power supply, nominal 3.3V 19 DIF 5 OUT 0.7V differential complement clock outputs 20 DIF 5 OUT 0.7V differential true clock outputs Active high input for enabling outputs. 21 OE 6 IN 0 = tri-state outputs, 1= enable outputs 22 DIF 6 OUT 0.7V differential complement clock outputs 23 DIF 6 OUT 0.7V differential true clock outputs 24 VDD PWR Power supply, nominal 3.3V 25 GND PWR Ground pin. This pin establishes the reference current for the differential current- mode output pairs. This pin requires a fixed precision resistor tied to 26 IREF OUT ground in order to establish the appropriate current. 475 ohms is the standard value. 27 GNDA PWR Ground pin for the PLL core. 28 VDDA PWR 3.3V power for the PLL core. 0767E12/14/07 2