DATASHEET TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 9DB233 Description Features/Benefits The 9DB233 zero-delay buffer supports PCIe Gen3 OE pins suitable for Express Card applications requirements, while being backwards compatible to PCIe PLL or bypass mode PLL can dejitter incoming clock Gen2 and Gen1. The 9DB233 is driven by a differential Selectable PLL bandwidth minimizes jitter peaking in SRC output pair from an IDT 932S421 or 932SQ420 or downstream PLL s equivalent main clock generator. It attenuates jitter on the Spread Spectrum Compatible tracks spreading input input clock and has a selectable PLL bandwidth to clock for low EMI maximize performance in systems with or without SMBus Interface allows control of PLL BW and Mode Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 Key Specifications clock request (OE ) pins make the 9DB233 suitable for Cycle-to-cycle jitter < 50 ps Express Card applications. Output-to-output skew < 50 ps Recommended Application PCIe Gen3 phase jitter < 1.0ps RMS 2 output PCIe Gen3 zero-delay/fanout buffer Output Features 2 - 0.7V current mode differential HCSL output pairs Block Diagram OE0 OE1 DIF 0 SRC IN SPREAD COMPATIBLE SRC IN PLL DIF 1 PLL BW CONTROL SMBDAT LOGIC SMBCLK IREF IDT TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 1 9DB233 OCTOBER 20, 20169DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 Pin Configuration PLL BW 1 20 VDDA SRC IN 2 19 GNDA SRC IN 3 18 IREF vOE0 4 17 vOE1 VDD 5 16 VDD GND 6 15 GND DIF 0 7 14 DIF 1 DIF 0 8 13 DIF 1 VDD 9 12 VDD SMBDAT 10 11 SMBCLK Note: Pins preceeded by v have internal 120K ohm pull down resistors Power Distribution Table Pin Number Description VDD GND 5,9,12,16 6,15 Differential Outputs 96 SMBUS 20 19 IREF 20 19 Analog VDD & GND for PLL core IDT TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 2 9DB233 OCTOBER 20, 2016 9DB233