7-Output 3.3V PCIe Fanout Buffer 9DBL07x1 DATASHEET Description Features/Benefits The 9DBL07x1 devices are 3.3V members of IDT s Direct connection to 100 (xx41) or 85 (xx51) Full-Featured PCIe clock family. The 9DBL07x1 devices transmission lines saves 28 resistors compared to support PCIe Gen14 Common Clocked (CC) and PCIe standard PCIe devices Separate Reference Independent Spread (SRIS) systems. 134mW typical power consumption eliminate thermal They offer a choice of integrated output terminations concerns providing direct connection to 85 or 100 transmission VDDIO allows 50% power savings at optional 1.05V lines. The 9DBL07P1 can be factory programmed with a maximum power savings user-defined power up default SMBus configuration. SMBus-selectable features allows optimization to customer requirements: Recommended Application control input polarity PCIe Gen14 clock distribution for Riser Cards, Storage, control input pull up/downs Networking, JBOD, Communications, Access Points slew rate for each output Output Features differential output amplitude 7 1-200 MHz Low-Power (LP) HCSL DIF pairs output impedance for each output 9DBL0741 default Zout = 100 Customer defined SMBus power up default can be programmed into P1 device allows exact optimization to 9DBL0751 default Zout = 85 customer requirements 9DBL07P1 factory programmable defaults OE pins support DIF power management Easy AC-coupling to other logic families, see IDT HCSL differential input can be driven by common clock application note AN-891. sources Key Specifications Spread Spectrum tolerant allows reduction of EMI DIF additive cycle-to-cycle jitter < 5ps Device contains default configuration SMBus interface not required for device operation DIF output-to-output skew < 50ps Three selectable SMBus addresses multiple devices can Additive phase jitter is 0ps (typical rms) for PCIe Gen14 easily share an SMBus segment CC, SRIS Space saving 40-pin 5 x 5mm VFQFPN minimal board Additive phase jitter 111fs rms typ. at 156.25M (1.5M to space 10M) Block Diagram vOE(6:0) 7 DIF6 CLK IN DIF5 CLK IN DIF4 vSADR DIF3 DIF2 CKPWRGD PD SDATA 3.3 DIF1 SCLK 3.3 DIF0 Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis. 9DBL07x1 AUGUST 1, 2017 1 2017 Integrated Device Technology, Inc. Control Logic9DBL07x1 DATASHEET Pin Configuration 40 39 38 37 36 35 34 33 32 31 vSADR tri130 NC OE6 229 vOE3 DIF6328 DIF3 DIF6 427 DIF3 VDDR3.3529DBL07x16 VDDIO CLK IN62epad is GND5 VDD3.3 CLK IN 724 vOE2 GNDDIG823 DIF2 SCLK 3.3922 DIF2 SDATA 3.3 10 21 vOE1 11 12 13 14 15 16 17 18 19 20 40-VFQFPN, 5x5mm 0.4mm pin pitch v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor prefix indicates internal 120KOhm pull up resistor SMBus Address Selection Table + Read/Write bit SADR Address 0 1101011 x State of SADR on first application of x M 1101100 CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin OEx bit True O/P Comp. O/P 1 1 0X X X Low Low 1 1 1 Running 0 X Low Low 1 Running 1 0 Running Running 1 1 1 Running 1 1 Low Low 1. The output state is set by B11 1:0 (Low/Low default) Power Connections Pin Number Description VDD VDDIO GND Input 541 receiver analog 11 8 Digital Power 16,25,31 12,17,26,32,39 41 DIF outputs 7-OUTPUT 3.3V PCIE FANOUT BUFFER 2 AUGUST 1, 2017 VDDDIG3.3 CKPWRGD PD VDDIO VDDIO vOE0 vOE5 DIF0 DIF5 DIF0 DIF5 VDD3.3 vOE4 VDDIO DIF4 DIF1 DIF4 DIF1 VDDIO NC VDD3.3