9DBU0231AKLF Renesas

2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB 9DBU0231 DATASHEET Description Features/Benefits The 9DBU0231 is a member of IDT s 1.5V Ultra-Low-Power LP-HCSL outputs save 4 resistors compared to standard (ULP) PCIe family. The device has 2 output enables for clock HCSL outputs management. 35mW typical power consumption in PLL mode eliminates thermal concerns Recommended Application Spread Spectrum (SS) compatible allows SS for EMI 1.5V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB) reduction OE pins support DIF power management Output Features HCSL compatible differential input can be driven by 2 1-167MHz Low-Power (LP) HCSL DIF pairs common clock sources SMBus-selectable features optimize signal integrity to Key Specifications application DIF cycle-to-cycle jitter <50ps slew rate for each output DIF output-to-output skew <50ps differential output amplitude DIF phase jitter is PCIe Gen1-2-3 compliant Pin/SMBus selectable PLL bandwidth and PLL Bypass DIF additive phase jitter is <100fs rms for PCIe Gen3 optimize PLL to application DIF additive phase jitter <350fs rms for 12k-20MHz Outputs blocked until PLL is locked clean system start-up Device contains default configuration SMBus interface not required for device control 3.3V tolerant SMBus interface works with legacy controllers Space saving 24-pin 4x4mm VFQFPN minimal board space Block Diagram vOE(1:0) 2 DIF1 CLK IN SS- Compatible DIF0 PLL vHIBW BYPM LOBW CKPWRGD PD CONTROL SDATA 3.3 LOGIC SCLK 3.3 9DBU0231 REVISION D 04/22/15 1 2015 Integrated Device Technology, Inc. CLK IN 9DBU0231 DATASHEET Pin Configuration 24 23 22 21 20 19 FB DNC 1 18 DIF1 VDDR1.5 2 17 DIF1 CLK IN 3 9DBU0231 VDDA1.5 16 CLK IN 4 GNDA 15 epad is Gnd GNDR 5 DIF0 14 GNDDIG 6 13 DIF0 7 8 9 10 11 12 24-pin VFQFPN, 4x4 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table + Read/Write bit Address 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin PLL OEx bit True O/P Comp. O/P 0 X X X Low Low Off 1 1 Running 0 X Low Low On 1 1 Running 1 0 Running Running On 1 1 Running 1 1 Low Low On 1. If Bypass mode is selected, the PLL will be off, and outputs will be running. Power Connections PLL Operating Mode Pin Number Byte1 7:6 Byte1 4:3 Description VDD GND HiBW BypM LoBW MODE Readback Control 25 Input receiver analog 0 PLL Lo BW 00 00 76 Digital Power MBypass 01 01 11,20 10,21 DIF outputs 1 PLL Hi BW 11 11 16 15 PLL Analog Note: epad on this device is not electrically connected to the die. It should be connected to ground for best thermal performance. 2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB 2 REVISION D 04/22/15 VDDDIG1.5 FB DNC SCLK 3.3 vHIBW BYPM LOBW SDATA 3.3 CKPWRGD PD GND GND VDDO1.5 VDDO1.5 vOE0 vOE1