2-Output 1.8V PCIe Zero Delay/Fanout 9DBV 0241 Clock Buffer with Zo = 100ohms D ATA S HE E T Description Features/Benefits The 9DBV0241 is a member of Renesas 1.8V LP-HCSL outputs with Zo = 100 saves 8 resistors Very-Low-Power (VLP) PCIe family. The device has 2 output compared to standard HCSL outputs enables for clock management. 35mW typical power consumption in PLL mode reduced thermal concerns Spread Spectrum (SS) compatible allows use of SS for Recommended Application EMI reduction 1.8V PCIe Gen15 Zero-Delay/Fan-out Buffer (ZDB/FOB) OE pins support DIF power management HCSL compatible differential input can be driven by Output Features common clock sources Two 1200MHz Low-Power (LP) HCSL DIF pairs with SMBus-selectable features optimize signal integrity to ZO = 100 application slew rate for each output Key Specifications differential output amplitude Pin/software selectable PLL bandwidth and PLL Bypass DIF cycle-to-cycle jitter < 50ps optimize PLL to application DIF output-to-output skew < 50ps Outputs blocked until PLL is locked clean system start-up PCIe Gen5 CC additive phase jitter < 40fs RMS Device contains default configuration SMBus interface not 12kHz20MHz additive phase jitter = 156fs RMS at required for device control 156.25MHz (typical) 3.3V tolerant SMBus interface works with legacy controllers Space saving 4 4mm 24-VFQFPN minimal board space Block Diagram y vOE(1:0) 2 CLK IN DIF1 SS- Compatible DIF0 PLL vHIBW BYPM LOBW CONTROL CKPWRGD PD LOGIC SDATA 3.3 SCLK 3.3 9DBV0241 R31DS0075EU0700 AUGUST 2, 2021 1 2021 Renesas Electronics Corporation CLK IN 9DBV0241 DATASHEET Pin Configuration 24 23 22 21 20 19 FB DNC 1 DIF1 18 VDDR1.8 2 DIF1 17 9DBV0241 CLK IN 3 16 VDDA1.8 CLK IN 4 GNDA 15 epad is GND GNDR 5 DIF0 14 GNDDIG 6 13 DIF0 7 8 9 10 11 12 24-pin VFQFPN, 4x4 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin PLL OEx bit True O/P Comp. O/P 0 X X X Low Low Off 1 1 Running 0 X Low Low On 1 1 Running 1 0 Running Running On 1 1 Running 1 1 Low Low On 1. If Bypass mode is selected, the PLL will be off, and outputs will be running. Power Connections PLL Operating Mode Pin Number Byte1 7:6 Byte1 4:3 Description VDD GND HiBW BypM LoBW MODE Readback Control 25 Input receiver analog 0 PLL Lo BW 00 00 76 Digital Power M Bypass 01 01 11,20 10,21 DIF outputs 1 PLL Hi BW 11 11 16 15 PLL Analog SMBus Address Address + Read/Write bit Frequency Select Table 1101101 x FSEL CLK IN DIFx Byte3 4:3 (MHz) (MHz) 00 (Default) 100.00 CLK IN 01 50.00 CLK IN 10 125.00 CLK IN 11 Reserved Reserved 2-OUTPUT 1.8V PCIE ZERO DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 2 R31DS0075EU0700 AUGUST 2, 2021 VDDDIG1.8 FB DNC SCLK 3.3 vHIBW BYPM LOBW SDATA 3.3 CKPWRGD PD GND GND VDDO1.8 VDDO1.8 vOE0 vOE1