9QXL2000BNLGI Renesas

9QXL2000B 20-Output DB2000Q Datasheet Description Features Low-Power HCSL (LP-HCSL) 85 outputs eliminate 80 The 9QXL2000B is a 20-output very-low-additive phase jitter 2 resistors, saving 130mm of area fanout buffer for PCIe Gen4 and Gen5. It offers integrated terminations for 85 transmission lines with individual output Low-Power HCSL (LP-HCSL) outputs reduce device power impedance trim and via SMBus registers. consumption by 50% 8 OE pins configurable to control up to 20 outputs PCIe Clocking Architectures 9 selectable SMBus addresses Spread spectrum compatible Common Clocked (CC) 10 10 mm 72-VFQFPN package Independent Reference (IR) with and without spread spectrum Output Features Typical Applications 20 Low-Power HCSL (LP-HCSL) 85 output pairs Servers Storage Key Specifications Networking SSDs Output-to-output skew: < 50ps Additive phase jitter: DB2000Q filter < 40fs rms Additive Phase jitter: PCIe Gen4 filter < 40fs rms Additive Phase jitter: PCIe Gen5 filter < 20fs rms DB2000Q v1.1 pinout Block Diagram VDDR VDD x 6 DIF IN DIF 19 DIF IN DIF 19 vSADR0 tri 20 vSADR1 tri SMBus Factory outputs Engine Configuration SMBCLK SMBDAT DIF 0 DIF 0 CKPWRGD PD Control Logic OE 5:12 GNDR EPAD/GND GND x 5 2021 Renesas Electronics Corporation 1 R31DS0049EU040 June 10, 20219QXL2000B Datasheet Contents Description 1 PCIe Clocking Architectures . 1 Typical Applications . 1 Features 1 Output Features 1 Key Specifications 1 Block Diagram . 1 Pin Assignments 3 Pin Descriptions 4 Absolute Maximum Ratings . 7 Electrical Characteristics . 7 Power Management 12 Power Connections 12 SMBus Addressing . 13 Test Loads . 14 Alternate Terminations 14 General SMBus Serial Interface Information . 15 Package Outline Drawings . 20 Ordering Information . 20 Marking Diagram 20 Revision History . 20 2021 Renesas Electronics Corporation 2 R31DS0049EU040 June 10, 2021