2:12 DB1200ZL Derivative for 9ZML1232E/9ZML1252E PCIe Gen14 and UPI Datasheet Description Features 2 configurable low drift I2O delays up to 2.9ns maintain The 9ZML1232E/9ZML1252E are a second generation transport delay for various topologies 2-input/12-output differential mux for Intel Purley and newer platforms. It exceeds the demanding DB1200ZL performance LP-HCSL outputs eliminate 24 resistors (9ZML1232E) specifications and is backwards compatible to the 9ZML1232B. It LP-HCSL outputs with Zout = 85 eliminate 48 resistors utilizes Low-Power HCSL-compatible outputs to reduce power (9ZML1252E) consumption and termination resistors. It is suitable for 9 selectable SMBus addresses multiple devices can share PCI-Express Gen14 or QPI/UPI applications, and provides 2 same SMBus segment configurable low-drift I2O settings, one for each input channel, to Separate VDDIO for outputs allows maximum power savings allow I2O tuning for various topologies. PLL or Bypass Mode PLL can dejitter incoming clock Hardware or software-selectable PLL BW minimizes jitter PCIe Clocking Architectures peaking in downstream PLLs Common Clocked (CC) Spread spectrum compatible tracks spreading input clock for Separate Reference No Spread (SRNS) EMI reduction Separate Reference Independent Spread (SRIS) SMBus interface software can modify device settings without hardware changes Typical Applications 10 10 mm 72-VFQFPN package small board footprint Servers, Storage, Networking, SSDs Key Specifications Output Features Cycle-to-cycle jitter < 50ps Output-to-output skew < 50ps 12 Low-power HCSL (LP-HCSL) output pairs (9ZML1232E) Input-to-output delay: Fixed at 0 ps 12 Low-power HCSL (LP-HCSL) output pairs with 85 Zout (9ZML1252E) Input-to-output delay variation < 50ps Phase jitter: PCIe Gen4 < 0.5ps rms Phase jitter: UPI > 9.6GB/s < 0.1ps rms Block Diagram I2O Low Phase FBOUT NC Delay Noise Z-PLL SEL A B (SS- Compatible) DIF 11 Bypass path 12 vHIBW BYPM outputs LOBW CKPWRGD PD vSMB A0 tri DIF 0 vSMB A1 tri SMBDAT NOTE: Internal series resistors are only present on the 9ZML1252 SMBCLK OE(11:0) 2021 Renesas Electronics Corporation 1 R31DS0025EU0500 May 12, 2021 DIF INA DIF INB CONTROL9ZML1232E/9ZML1252E Datasheet Contents Description 1 PCIe Clocking Architectures . 1 Typical Applications . 1 Output Features 1 Features 1 Key Specifications 1 Block Diagram . 1 Pin Configuration . 3 Power Management 3 PLL Operating Mode 3 Power Connections (for pin compatibility with 9ZML12xxB) 3 Power Connections . 3 Skew Programming . 3 Pin Descriptions 4 Absolute Maximum Ratings . 6 Electrical Characteristics . 6 DIF IN Clock Input Parameters . 6 SMBus . 6 Input/Supply/Common Parameters . 7 DIF HCSL/LP-HCSL Outputs . 8 Current Consumption . 8 Skew and Differential Jitter Parameters . 9 Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures 10 Filtered Phase Jitter Parameters - PCIe Separate Reference Independent Spread (SRIS) Architectures 11 Filtered Phase Jitter Parameters - QPI/UPI . 11 Unfiltered Phase Jitter Parameters - 12kHz to 20MHz . 12 Clock PeriodsDifferential Outputs with Spread Spectrum Disabled . 12 Clock PeriodsDifferential Outputs with Spread Spectrum Enabled . 12 Test Loads . 12 General SMBus Serial Interface Information . 13 Package Outline Drawings . 16 Ordering Information . 16 Marking Diagrams . 16 Revision History . 17 2021 Renesas Electronics Corporation 2 R31DS0025EU0500 May 12, 2021