9ZXL06x2E/9ZXL08xxE/ 6 to 12-Output Buffers for PCIe 9ZXL12x2E Gen15 and UPI with SMBus Write Protect Datasheet Description Features SMBus Write Protect pin prevents SMBus against accidental The 9ZXL revision E family of Zero-Delay/Fanout Buffers (ZDB, writes FOB) with SMBus Write Protect are 2nd-generation enhanced performance buffers for PCIe and CPU applications. The devices 612 Low-power HCSL (LP-HCSL) outputs have hardware SMBUS write protection to prevent accidental Integrated terminations eliminate up to 4 resistors per output writes. The family meets all published QPI/UPI, DB2000Q and pair PCIe Gen15 jitter specifications. Devices range from 6 to 12 Dedicated OE pins support PCIe CLKREQ function outputs, with each output having an OE pin to support the PCIe Up to 9 selectable SMBus addresses (9ZXL12xx, 9ZXL0853) CLKREQ function for low power states. All devices meet DB2000Q, DB1200ZL and DB800ZL jitter and skew requirements. Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topologies PCIe Clocking Architectures Hardware/SMBus control of ZDB and FOB modes allow change without power cycle Common Clocked (CC) Spread spectrum compatible Independent Reference (IR) with and without spread spectrum (SRIS, SRNS) 1400MHz FOB operation (all devices) 100MHz and 133.33MHz ZDB mode (9ZXL12xx, 9ZXL08xx) Key Specifications 100MHz ZDB mode (9ZXL06xx) Fanout Buffer Mode additive phase jitter: -40C to +85C operating temperature range PCIe Gen5 CC, UPI > 20Gb/s < 24fs RMS Packages: See Ordering Information for more details DB2000Q additive jitter < 39fs RMS Typical Applications QPI/UPI 11.4GB/s < 40fs RMS IF-UPI additive jitter < 70fs RMS Servers/High-performance Computing ZDB Mode phase jitter: nVME Storage PCIe Gen5 CC, UPI > 20Gb/s < 22fs RMS Networking QPI/UPI 11.4GB/s < 120fs RMS Accelerators IF-UPI additive jitter < 130fs RMS Industrial Control Cycle-to-cycle jitter < 50ps Output-to-output skew < 50ps Block Diagram VDDR VDDA VDD VDDIO 9ZXL12xx only FBOUT NC FBOUT NC PLL DIF IN DIFn 9ZXL12x2 DIF IN DIFn 9ZXL08x2 9ZXL08x3 only 100M 133M 9ZXL12x2 vSADR1 tri 12, 8, or 6 9ZXL08x3 outputs vSADR0 tri SMBus Factory only SMBCLK Engine Configuration SMBDAT vSMB WRTLOCK DIF0 vHIBW BYPM-LOBW DIF0 CKPWRGD PD Control Logic vOE n:0 Resistors are integrated on 9ZXLxx5x devices and external on 9ZXLxx3x devices GNDA GND 2020 Renesas Electronics Corporation 1 August 25, 20209ZXL06x2E/9ZXL08xxE/9ZXL12x2E Datasheet Contents Description 1 PCIe Clocking Architectures . 1 Key Specifications 1 Features 1 Typical Applications . 1 Block Diagram . 1 Pin Assignments 3 9ZXL06x2E Pin Assignment 3 9ZXL08x2E Pin Assignment 4 9ZXL0853E Pin Assignment 5 9ZXL12x2E Pin Assignment 6 Pin Descriptions 7 Absolute Maximum Ratings 10 Thermal Characteristics . 10 Electrical Characteristics 11 Power Management 19 Test Loads . 20 General SMBus Serial Interface Information . 22 How to Write . 22 How to Read . 22 Package Outline Drawings . 26 Marking Diagrams . 26 9ZXL06x2E 26 9ZXL08xxE 27 9ZXL12x2E 27 Ordering Information . 28 Revision History . 29 2020 Renesas Electronics Corporation 2 August 25, 2020