DATASHEET CA3420 FN1320 Rev 9.00 0.5MHz, Low Supply Voltage, Low Input Current BiMOS Operational Amplifier Oct 4, 2005 The CA3420 is an integrated circuit operational amplifier that Features combines PMOS transistors and bipolar transistors on a 2V Supply at 300 A Supply Current single monolithic chip. The CA3420 BiMOS operational amplifier features gate protected PMOS transistors in the 1pA Input Current (Typ) (Essentially Constant to 85C) input circuit to provide very high input impedance, very low Rail-to-Rail Output Swing (Drive 2mA into 1k Load) input currents (less than 1pA). The internal bootstrapping Pin Compatible with 741 Operational Amplifiers network features a unique guardbanding technique for reducing the doubling of leakage current for every 10C Pb-Free Plus Anneal Available (RoHS Compliant) increase in temperature. The CA3420 operates at total supply voltages from 2V to 20V either single or dual supply. Applications This operational amplifier is internally phase compensated to pH Probe Amplifiers achieve stable operation in the unity gain follower configuration. Additionally, it has access terminals for a Picoammeters supplementary external capacitor if additional frequency roll- Electrometer (High Z) Instruments off is desired. Terminals are also provided for use in Portable Equipment applications requiring input offset voltage nulling. The use of PMOS in the input stage results in common mode input Inaccessible Field Equipment voltage capability down to 0.45V below the negative supply Battery-Dependent Equipment (Medical and Military) terminal, an important attribute for single supply application. The output stage uses a feedback OTA type amplifier that Functional Diagram can swing essentially from rail-to-rail. The output driving current of 1.5mA (Min) is provided by using nonlinear current mirrors. X1 Ordering Information PART PART TEMP. PKG. NUMBER MARKING RANGE (C) PACKAGE DWG. - MOS CA3420E CA3420E -55 to 125 8 Ld PDIP E8.3 BIPOLAR CA3420EZ CA3420EZ -55 to 125 8 Ld PDIP* E8.3 MOS + BIPOLAR (Note) (Pb-free) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder X1 processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and BUFFER AMPS 100% matte tin plate termination finish, which are RoHS compliant BOOTSTRAPPED HIGH GAIN OTA BUFFER and compatible with both SnPb and Pb-free soldering operations. INPUT PROTECTION (50K) (X2) Intersil Pb-free products are MSL classified at Pb-free peak reflow NETWORK temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinout CA3420 (PDIP) TOP VIEW 1 8 OFFSET NULL STROBE INV. 2 7 V+ INPUT - + NON-INV. 3 6 OUTPUT INPUT 4 5 OFFSET NULL V- FN1320 Rev 9.00 Page 1 of 5 Oct 4, 2005CA3420 Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to V-) .22V Thermal Resistance (Typical, Note 2) (C/W) (C/W) JA JC Differential Input Voltage .15V PDIP Package* 105 N/A DC Input Voltage (V+ + 8V) to (V- -0.5V) Maximum Junction Temperature (Plastic Package) . 150C Input Current . 1mA Maximum Storage Temperature Range -65C to 150C Output Short Circuit Duration (Note 1) Indefinite Maximum Lead Temperature (Soldering 10s) 300C *Pb-free PDIPs can be used for through hole wave solder processing Operating Conditions only. They are not intended for use in Reflow solder processing Temperature Range . -55C to 125C applications. CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. is measured with the component mounted on an evaluation PC board in free air. JA Electrical Specifications Typical Values Intended Only for Design Guidance, V = 10V, T = 25C SUPPLY A PARAMETER SYMBOL TEST CONDITIONS TYP UNITS Input Resistance R 150 T I Input Capacitance C 4.9 pF I Output Resistance R 300 O Equivalent Input Noise Voltage e f = 1kHz R = 100 62 nV/ Hz N S f = 10kHz 38 nV/ Hz Short-Circuit Current Source I+2.6mA OM To Opposite Supply Sink I-2.4mA OM Gain Bandwidth Product f 0.5 MHz T Slew Rate SR 0.5 V/s Transient Response Rise Time t R = 2k , C = 100pF 0.7 s R L L Overshoot OS 15 % Current from Terminal 8 To V- I+20 A 8 To V+ I-2mA 8 Electrical Specifications For Equipment Design, At V = 1V, T = 25C, Unless Otherwise Specified SUPPLY A TEST PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Offset Voltage V - 5 10 mV IO Input Offset Current (Note 3) I - 0.01 4 pA IO Input Current (Note 3) I -15pA I Large Signal Voltage Gain A R = 10k 10 100 - kV/V OL L 80 100 - dB Common Mode Rejection Ratio CMRR - 560 1800 V/V 55 65 - dB Common Mode Input Voltage Range V+0.20.5- V lCR V---1.3- V lCR Power Supply Rejection Ratio PSRR V / V - 100 1000 V/V IO 60 80 - dB Max Output Voltage V +R = 0.90 0.95 - V OM L V - -0.85 -0.91 - V OM Supply Current I+ - 350 650 A Device Dissipation P -0.7 1.1 mW D Input Offset Voltage Temperature Drift V / T- 4- V/C lO NOTE: 3. The maximum limit represents the levels obtainable on high speed automatic test equipment. Typical values are obtained under laboratory conditions. FN1320 Rev 9.00 Page 2 of 5 Oct 4, 2005