8T49N1012 Evaluation Board USER GUIDE Introduction The 8T49N1012 evaluation board user guide is intended to help the user power-up and quick-start the 8T49N1012 evaluation board. The scope of the user guide is limited to the physical connectivity of the board and does not address the programming section of it. This guide will model two set-ups: Set-up 1 will use a clock generator as input and Set-up 2 will use a crystal as input source. Set-up 1: Set-up 2: CLK/nCLK will be used as input OSCI/OSCO will be used as input Q0/nQ0 will be used as output Q0/nQ0 will be used as output Board Overview Use Figure 1 to identify the power supply jacks, input and output SMA connectors, USB connector, crystal, power selection jumpers, dip switch, device under test, EEPROM, Reset button, CLK/nCLK Inputs and Ref Out. Figure 1. 8T49N1012 Evaluation Board Top View MARCH 30, 2016 1 2016 Integrated Device Technology, Inc.8T49N1012 EVALUATION BOARD Requirements Power supply with 4V and ~800mA rating Signal generator (10MHz to 600MHz Input and an amplitude from 0.4V to 0.8V) or crystal Signal analyzer Two banana plug cables (red and black) to connect the power supply source to the board Two SMA cables to connect the signal generator to the CLK/nCLK inputs Two SMA cables to connect Q0/nQ0 to the signal analyzer 50 to ground terminators to terminate the unused outputs USB cable to connect the board to a laptop and program the device DIP Switch Pin Table 1: DIP Switch Pin Description Pin Name Description CLK SEL Clock select pin. 0: CLK/nCLK 1: XTAL (Default) OE1 Output enable. LVCMOS/LVTTL interface levels OE0 Output enable. LVCMOS/LVTTL interface levels. PLL BYP Bypass Selection. Allow PLL references to bypass PLL and appear at Q 0:3 . LVTTL / LVCMOS interface levels. 2 2 nI C/SPI Serial Interface Mode Selection. LVCMOS Input Levels: 0 = I C Mode 1 = SPI Mode SCAN MODE (Factory Use Only) 2 SA1 I C lower address bit A1 / SPI interface serial data input signal. 2 SA0 I C lower address bit A0 / SPI interface chip select signal. LegendEvaluation Board Inputs CLK/nCLK Clock input lines. Can accept LVPECL, LVDS, LVHSTL, HCSL or LVCMOS input clock. OSCI/OSCO Crystal input lines. Outputs Q0/nQ0 Can be a differential pair or two individual single-ended outputs. Q1/nQ1 Can be a differential pair or two individual single-ended outputs. Q2/nQ2 Can be a differential pair or two individual single-ended outputs. Q3/nQ3 Can be a differential pair or two individual single-ended outputs. Q4/nQ4 Can be a differential pair or two individual single-ended outputs. Q5/nQ5 Can be a differential pair or two individual single-ended outputs. Q6/nQ6 Can be a differential pair or two individual single-ended outputs. Q7/nQ7 Can be a differential pair or two individual single-ended outputs. Q8/nQ8 Can be a differential pair or two individual single-ended outputs. Q9/nQ9 Can be a differential pair or two individual single-ended outputs. Q10/nQ10 Can be a differential pair or two individual single-ended outputs. Q11/nQ11 Can be a differential pair or two individual single-ended outputs. MARCH 30, 2016 2