DATASHEET HM-65642 FN3005 Rev 2.00 8K x 8 Asynchronous CMOS Static RAM May 2002 Features Description Full CMOS Design The HM-65642 is a CMOS 8192 x 8-bit Static Random Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide Six Transistor Memory Cell standard, which allows easy memory board layouts which Low Standby Supply Current . 100A accommodate a variety of industry standard ROM, PROM, Low Operating Supply Current .20mA EPROM, EEPROM and RAMs. The HM-65642 is ideally suited for use in microprocessor based systems. In particu- Fast Address Access Time 150ns lar, interfacing with the Intersil 80C86 and 80C88 micropro- Low Data Retention Supply Voltage 2.0V cessors is simplified by the convenient output enable (G) CMOS/TTL Compatible Inputs/Outputs input. JEDEC Approved Pinout The HM-65642 is a full CMOS RAM which utilizes an array Equal Cycle and Access Times of six transistor (6T) memory cells for the most stable and No Clocks or Strobes Required lowest possible standby supply current over the full military temperature range. Gated Inputs No Pull-Up or Pull-Down Resistors Required Easy Microprocessor Interfacing Dual Chip Enable Control Ordering Information TEMPERATURE (NOTE 1) (NOTE 1) (NOTE 1) PACKAGE RANGE 150ns/75 A 150ns/150 A 200ns/250 A PKG. NO. o o CERDIP -40 C to +85 C - HM1-65642-9 - F28.6 o o JAN -55 C to +125 C 29205BXA - - F28.6 NOTE: 1. Access Time/Data Retention Supply Current. Pinout HM-65642 (CERDIP) TOP VIEW 1 28 NC V PIN DESCRIPTION CC 2 27 A12 W A Address Input 3 26 A7 E2 DQ Data Input/Output 4 25 A6 A8 E1 Chip Enable 5 A5 24 A9 E2 Chip Enable 6 23 A4 A11 7 A3 22 G W Write Enable 8 A2 21 A10 G Output Enable 9 20 A1 E1 NC No Connections 10 A0 19 DQ7 GND Ground 11 18 DQ0 DQ6 V Power CC 12 DQ1 17 DQ5 13 DQ2 16 DQ4 GND 14 15 DQ3 FN3005 Rev 2.00 Page 1 of 8 May 2002HM-65642 Functional Diagram A9 A A8 A12 8 256 A7 256 x 256 MEMORY ARRAY A6 A A5 A4 8 A3 256 A2 A A1 5 COLUMN SELECT A0 (8 OF 256) A A10 A11 5 8 W G E1 8 E2 DQ 1 OF 8 TRUTH TABLE MODE E1 E2 W G Standby (CMOS) X GND X X Standby (TTL) V XXX IH XV XX IL Enable (High Z) V V V V IL IH IH IH Write V V V X IL IH IL Read V V V V IL IH IH IL FN3005 Rev 2.00 Page 2 of 8 May 2002 COLUMN ROW ADDRESS BUFFERS ADDRESS BUFFERS ROW DECODER