DATA SHEET MC100ES6221 Freescale Semiconductor Rev 5, 04/2005 Technical Data MC100ES6221 Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Low Voltage 1:20 Differential Fanout Buffer MC100ES6221 ECL/PECL/HSTL Clock Fanout Buffer PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES (JUNE 30, 2014) The MC100ES6221 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6221 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential LOW VOLTAGE DUAL architecture, the device offers very low skew outputs and superior digital signal 1:20 DIFFERENTIAL ECL/PECL/HSTL characteristics. Target applications for this clock driver is high performance clock CLOCK FANOUT BUFFER distribution in computing, networking and telecommunication systems. Features 1:20 differential clock fanout buffer 100 ps maximum device skew SiGe technology Supports DC to 2 GHz operation of clock or data signals TB SUFFIX 52-LEAD LQFP PACKAGE ECL/PECL compatible differential clock outputs EXPOSED PAD ECL/PECL/HSTL compatible differential clock inputs CASE 1336A-01 Single 3.3 V, 3.3 V, 2.5 V or 2.5 V supply Standard 52 lead LQFP package with exposed pad for enhanced thermal characteristics Supports industrial temperature range Pin and function compatible to the MC100EP221 AE SUFFIX 52-lead Pb-free Package Available 52-LEAD LQFP PACKAGE Pb-FREE PACKAGE Functional Description CASE 1336A-01 The MC100ES6221 is designed for low skew clock distribution systems and supports clock frequencies up to 2 GHz. The device accepts two clock sources. The CLK0 input can be driven by ECL or PECL compatible signals, the CLK1 input accepts HSTL compatible signals. The selected input signal is distributed to 20 identical, differential ECL/PECL outputs. If V is connected to the CLK0 or CLK1 input BB and bypassed to GND by a 10 nF capacitor, the MC100ES6221 can be driven by single-ended ECL/PECL signals utilizing the V bias voltage output. BB In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6221 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the MC100ES6221 supports positive (PECL) and negative (ECL) supplies. The MC100ES6221 is pin and function compatible to the MC100EP221. IDT Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer MC100ES6221 Freescale Semiconductor, Inc., 2005. All rights reserved. Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 1MC100ES6221 Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer NETCOM Q0 Q0 Q1 39 38 37 36 35 34 33 32 31 30 29 28 27 Q1 V 40 26 CC V Q12 CC Q2 41 25 Q2 Q5 Q12 CLK0 Q3 42 24 Q5 Q13 CLK0 Q3 43 23 Q4 Q13 44 22 0 Q4 Q14 V EE 45 21 MC100ES6221 Q3 Q14 1 46 20 Q3 Q15 V CC 47 19 Q2 Q15 CLK1 Q16 48 18 Q2 Q16 Q16 CLK1 49 17 Q17 Q1 Q16 Q17 50 16 Q1 Q17 Q18 V EE 51 15 Q18 Q0 Q17 52 14 Q19 Q0 V CC 1 234 567 89 10 11 12 13 Q19 CLK SEL V BB V EE Figure 1. MC100ES6221 Logic Diagram Figure 2. 52-Lead Package Pinout (Top View) Table 1. Pin Configuration Pin I/O Type Function CLK0, CLK0 Input ECL/PECL Differential reference clock signal input CLK1, CLK1 Input HSTL Alternative differential reference clock signal input CLK SEL Input ECL/PECL Reference clock input select QA 019 , QA 019 Output ECL/PECL Differential clock outputs (1) V Supply Negative power supply EE V Supply Positive power supply. All V pins must be connected to the positive CC CC power supply for correct DC and AC operation. V Output DC Reference voltage output for single ended ECL and PECL operation BB 1. In ECL mode (negative power supply mode), V is either 3.3 V or 2.5 V and V is connected to GND (0 V). In PECL mode (positive EE CC power supply mode), V is connected to GND (0 V) and V is either +3.3 V or +2.5 V. In both modes, the input and output levels are EE CC referenced to the most positive supply (V ). CC Table 2. Function Table Pin 0 1 CLK SEL CLK0, CLK0 input pair is the reference clock. CLK0 can be CLK1, CLK1 input pair is the reference clock. CLK1 can be driven by ECL or PECL compatible signals. driven by HSTL compatible signals. MC100ES6221 IDT Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer MC100ES6221 Advanced Clock Drivers Devices Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 2 Freescale Semiconductor 2 V Q6 CC V Q6 CC CLK SEL Q7 CLK0 Q7 CLK0 Q8 V BB Q8 CLK1 Q9 CLK1 Q9 Q10 V EE Q19 Q10 Q19 Q11 Q11 Q18 V Q18 CC