DATASHEET MULTIPLIER AND ZERO DELAY BUFFER MK2302-01 Description Features The MK2302-01 is a high performance Zero Delay Buffer 8-pin SOIC package (ZDB) which integrates IDTs proprietary analog/digital Pb (lead) free package Phase Locked Loop (PLL) techniques. The chip is part of Low input to output skew of 250 ps max TM IDTs ClockBlocks family and was designed as a Absolute jitter 500 ps performance upgrade to meet todays higher speed and Propagation Delay 350 ps lower voltage requirements. The zero delay feature means Ability to choose between different multipliers from 0.5X that the rising edge of the input clock aligns with the rising to 16X edges of both output clocks, giving the appearance of no Output clock frequency up to 168 MHz at 3.3 V delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other output. Can recover degraded input clock duty cycle Output clock duty cycle of 45/55 The MK2302-01 is ideal for synchronizing outputs in a large Full CMOS clock swings with 25mA drive capability at variety of systems, from personal computers to data TTL levels communications to graphics/video. By allowing off-chip Advanced, low power CMOS process feedback paths, the device can eliminate the delay through Operating voltage of 3.3 V or 5 V other devices. Industrial temperature version available Block Diagram ICLK Phase VCO CLK1 Detector, S1:0 Charge /2 Pump, and Loop CLK2 Filter divide FBIN by N External feedback can com e from CLK1 or CLK2 (see table on page 2) IDT MULTIPLIER AND ZERO DELAY BUFFER 1 MK2302-01 REV G 051310MK2302-01 MULTIPLIER AND ZERO DELAY BUFFER ZDB AND MULTIPLIER Pin Assignment FBIN 88 11 CLK2 ICLK 22 77 VDD GNDGND 33 66 CLK1 S0 44 55 S1 8 pin (150 mil) SOIC Clock Multiplier Decoding Table 1 (Multiplies Input clock by shown amount) FBIN S1 S0 CLK1 CLK2 CLK1 0 0 2 X ICLK ICLK CLK1 0 1 4 X ICLK 2 X ICLK CLK1 1 0 ICLK ICLK/2 CLK1 1 1 8 X ICLK 4 X ICLK CLK2 0 0 4 X ICLK 2 X ICLK CLK2 0 1 8 X ICLK 4 X ICLK CLK2 1 0 2 X ICLK ICLK CLK2 1 1 16 X ICLK 8 XICLK Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 FBIN Input Feedback clock input. 2 ICLK Input Reference clock input. 3 GND Power Connect to ground. 4 S0 Input Select 0 for output clock per decoding table above. Pull-up. 5 S1 Input Select 1 for output clock per decoding table above. Pull up. 6 CLK1 Output Clock output per table above. 7 VDD Power Connect to +3.3 V or +5.0 V. 8 CLK2 Output Clock output per table above. Low skew divide by two of pin 6 clock. IDT MULTIPLIER AND ZERO DELAY BUFFER 2 MK2302-01 REV G 051310