Low-Cost, 3.3V Zero Delay Buffer MPC962305 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 DATASHEET The MPC962309 is a zero delay buffer designed to distribute high-speed clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one MPC962305 reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin MPC962309 version of the MPC962309 which drives five outputs with one reference input. The -1H versions of these devices have higher drive than the -1 devices and can operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs which EF SUFFIX 8-LEAD SOIC PACKAGE lock to an input clock presented on the REF pin. The PLL feedback is on-chip and Pb-FREE PACKAGE is obtained from the CLOCKOUT pad. CASE 751-06 Features EJ SUFFIX 1:5 LVCMOS zero-delay buffer (MPC962305) 8-LEAD TSSOP PACKAGE Pb-FREE PACKAGE 1:9 LVCMOS zero-delay buffer (MPC962309) CASE 948J-01 Zero input-output propagation delay Multiple low-skew outputs EF SUFFIX 16-LEAD SOIC PACKAGE 250 ps max output-output skew Pb-FREE PACKAGE 700 ps max device-device skew CASE 751B-05 Supports a clock I/O frequency range of 10 MHz to 133 MHz, compatible with CPU and PCI bus frequencies Low jitter, 200 ps max cycle-cycle, and compatible with Pentium based systems Test Mode to bypass PLL (MPC962309 only. See Table 3) EJ SUFFIX 16-LEAD TSSOP PACKAGE 8-pin SOIC or 8-pin TSSOP package (MPC962305) 16-pin SOIC or 16-pin Pb-FREE PACKAGE TSSOP package (MPC962309), all Pb-free CASE 948F-01 Single 3.3 V supply Ambient temperature range: 40C to +85 C Compatible with the CY2305, CY23S05, CY2309, CY23S09 Spread spectrum compatible For drop in replacement for MPC962305 use 2305 For drop in replacement for MPC962309 use 2309 The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0 A of current draw for the device. The PLL shuts down in one additional case as shown in Table 3. Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this situation, the difference between the output skews of two devices will be less than 700 ps. All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to be less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps. The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information page. The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and MPC962309-1H, are available to provide faster rise and fall times of the base device. Pentium II is a trademark of Intel Corporation. MPC962305 REVISION 8 3/15/16 1 2016 Integrated Device Technology, Inc.MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr Block Diagram Pin Configuration SOIC/TSSOP Top View CLKOUT PLL REF 1 CLKOUT 16 MUX CLKA1 2 CLKA4 15 CLKA1 CLKA2 3 CLKA3 14 REF CLKA2 V V 4 13 DD DD GND 5 12 GND CLKA3 CLKB1 6 11 CLKB4 CLKA4 7 CLKB2 10 CLKB3 S2 8 S1 9 CLKB1 SOIC/TSSOP S2 Top View Select Input CLKB2 REF 1 CLKOUT 8 Decoding S1 CLKB3 CLK2 2 CLK4 7 CLK1 3 V 6 CLKB4 DD GND CLK3 4 5 Table 1. Pin Description for MPC962309 Pin Signal Description (1) 1REF Input reference frequency, 5 V-tolerant input (2) 2 CLKA1 Buffered clock output, Bank A (2) 3 CLKA2 Buffered clock output, Bank A 4V 3.3 V supply DD 5 GND Ground (2) 6 CLKB1 Buffered clock output, Bank B (2) 7 CLKB2 Buffered clock output, Bank B (3) 8S2 Select input, bit 2 (3) 9S1 Select input, bit 1 (2) 10 CLKB3 Buffered clock output, Bank B (2) 11 CLKB4 Buffered clock output, Bank B 12 GND Ground 13 V 3.3 V supply DD (2) 14 CLKA3 Buffered clock output, Bank A (2) 15 CLKA4 Buffered clock output, Bank A (2) 16 CLKOUT Buffered output, internal feedback on this pin 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. Table 2. Pin Description for MPC962305 Pin Signal Description (1) 1 REF Input reference frequency, 5 V-tolerant input (2) 2 CLK2 Buffered clock output (2) 3 CLK1 Buffered clock output 4 GND Ground (2) 5 CLK3 Buffered clock output 6 V 3.3 V supply DD (2) 7 CLK4 Buffered clock output (2) 8 CLKOUT Buffered clock output, internal feedback on this pin 1. Weak pull-down. 2. Weak pull-down on all outputs. MPC962305 REVISION 8 3/15/16 2 2016 Integrated Device Technology, Inc.