DATASHEET ZL2102 FN8440 Rev 2.00 6A Digital Integrated Synchronous Step-Down DC/DC Regulator with Auto November 20, 2014 Compensation The ZL2102 is an integrated digital power regulator with auto Features compensation and power management functions in a small Integrated MOSFET switches package, resulting in a flexible and integrated solution, which can be configured using the PowerNavigator graphical user 6A continuous output current interface. This synchronous buck converter operates from a Adjustable 0.54V to 5.5V output range 4.5V to 14V input supply and provides from 0.54V to 5.5V 4.5V to 14V input range output voltage at up to 6A. Up to 90% efficiency The ZL2102 can be configured for most applications using only hardware pin straps to adjust switching frequency, output Auto compensation for fast transient response voltage, UVLO, soft-start ramp/delay settings, sequencing SMBus compliant serial interface options, and SMBus address. For more advanced Snapshot parametric capture configurations, the ZL2102 supports over 70 PMBus commands. Output voltage/current is factory calibrated. Internal nonvolatile memory Internal synchronous power MOSFETs enable the ZL2102 to Small footprint QFN package (6mmx6mm) deliver continuous loads up to 6A with high efficiency. An internal Schottky bootstrap diode reduces discrete component Applications count. The ZL2102 also supports phase spreading to reduce Servers/storage equipment system input capacitance. Telecom/datacom equipment The ZL2102 uses the SMBus with PMBus protocol for Power supplies (memory, DSP, ASIC, FPGA) communication with a host controller and the Intersil s proprietary Digital-DC bus for interoperability between other Related Literature Intersil devices. AN2010Thermal and Layout Guidelines for Digital-DC Product AN2035Compensation Using CompZ TB389PCB Land Pattern and Surface Mount Guidelines for QFN Package V2P5 10F DDC Bus DDC VRA 4.7F SCL INTERFACE SMBus 4.7F VR SDA ZL2102 SALRT VDDS V IN VDDP 12V PG C B C IN HARDWARE MGN 0.1F 100F CONTROL BST EN L OUT 2.2H V OUT 3.3V SW SYNC 6A VSEN VSET COUT PGND SA 200F HARDWARE CONFIG SGND FC DGND CFG ePAD SS FIGURE 1. TYPICAL APPLICATION DIAGRAM FN8440 Rev 2.00 Page 1 of 58 November 20, 2014ZL2102 Table of Contents Pin Configuration 3 Pin Description 4 Ordering Information 4 Absolute Maximum Ratings . 5 Thermal Information . 5 Recommended Operating Conditions 5 Electrical Specifications . 5 Typical Performance Curves 7 Digital-DC Architecture Overview 8 Power Conversion Overview . 9 Power Management Overview . 9 Functional Description and Configuration .9 SMBus Device Address Selection (SA) 10 Output Voltage and VOUT MAX Selection (VSET) . 11 Automatic Loop Compensation (FC) 11 Synchronization and Sequencing Configuration Settings (CFG) . 12 Switching Frequency Setting (SYNC) 12 Soft-Start and UVLO Settings (SS) 13 Start-up Procedure . 13 Power-Good 14 Power Management Function Description 14 Input Undervoltage Lockout . 14 Output Overvoltage Protection . 14 Output Prebias Protection 14 Output Overcurrent Protection . 15 Thermal Overload Protection 15 Voltage Margining . 15 Digital-DC Bus 15 Phase Spreading 15 Output Sequencing 16 Fault Spreading . 16 Monitoring via SMBus 16 Nonvolatile Memory . 16 Snapshot Parametric Capture . 16 Power Train Component Selection . 17 Design Goal Trade-offs . 17 Inductor Selection . 17 Output Capacitor Selection 17 Input Capacitor 18 PCB Layout Recommendation 18 PMBus Command Summary 19 PMBus Data Formats 21 PMBus Command Detail 22 Revision History 57 About Intersil 57 Package Outline Drawing 58 FN8440 Rev 2.00 Page 2 of 58 November 20, 2014