RT9040 DDR Termination Regulator General Description Features zz z zz V Input Voltage Range : 1.1V to 3.5V IN The RT9040 is a sink/source tracking termination regulator. zz z zz V Input Voltage Range : 2.375V to 5.5V CNTL It is specifically designed for low-cost and low-external zz z zz MLCC Stable component count systems. The RT9040 possesses a high zz z zz PGOOD to Monitor Output Regulation speed operating amplifier that provides fast load transient zz z zz 10mA Reference (REFOUT) response and only requires a minimum 20F of ceramic zz z zz Meet DDRI, DDRII JEDEC Spec Supports DDRIII, Low output capacitance. The RT9040 supports remote sensing Power DDRIII / DDRIV VTT Application functions and all features required to power the DDRI / zz z zz Soft Start Function UVLO and OCP DDRII / DDRIII and Low Power DDRIII / DDRIV VTT bus zz z zz UVLO and OCP Protection termination according to the JEDEC specification. In zz z zz Thermal Shutdown addition, the RT9040 provides an open drain PGOOD signal zz z zz RoHS Compliant and Halogen Free to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) Application for DDR applications . z Notebook/Desktop/Server The RT9040 is available in the thermal efficient WDFN- z Telecom/Datacom, GSM Base Station, LCD-TV/PDP- 10L 3x3 package. TV ,Copier/Printer, Set-Top Box Ordering Information Pin Configurations (2) RT9040 (TOP VIEW) Pin 1 Orientation 10 REFIN 1 VCNTL (2) : Quadrant 2, Follow EIA-481-D 9 VIN 2 PGOOD 3 VOUT 8 GND Package Type 4 7 EN PGND 11 SENSE 5 6 REFOUT QW : WDFN-10L 3x3 (W-Type) WDFN-10L 3x3 Lead Plating System G : Green (Halogen Free and Pb Free) Marking Information Z : ECO (Ecological Element with Halogen Free and Pb free) RT9040GQW(2) Note : G4= : Product Code Richtek products are : YMDNN : Date Code G4=YM RoHS compliant and compatible with the current require- DNN ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. RT9040ZQW(2) G4 : Product Code YMDNN : Date Code G4 YM DNN DS9040-03 July 2011 www.richtek.com 1 GNDRT9040 Typical Application Circuit RT9040 2 10 VCNTL V VIN VCNTL IN 2.5V/3.3V/5V R1 C4 10k 4.7F 1 R3 REFIN 100k C1 9 PGOOD R2 C2 Power Good Indicator 10F x 2 1nF 10k 3 VOUT V OUT 5 C5 SENSE 6 10F x 3 REFOUT REFOUT 4 PGND C3 0.1F 7 Chip Enable EN 8, 11 (Exposed Pad) GND Functional Pin Description Pin No. Pin Name Pin Function 1 REFIN Reference Input. 2 VIN Supply Voltage for the LDO. 3 VOUT Power Output for the LDO. 4 PGND Power Ground Output for the LDO. Voltage Sense Output for the LDO. Connect to positive terminal of the output 5 SENSE capacitor or the load. 6 REFOUT Reference Output. Connect to GND through 0.1uF ceramic capacitor. Chip Enable. For DDR VTT application, connect EN to SLP S3. For any other 7 EN application(s), use EN as the ON/OFF function. Signal Ground. Connect to negative terminal of the output capacitor. The exposed 8, GND pad must be soldered to a large PCB and connected to GND for maximum power 11 (Exposed Pad) dissipation. PGOOD Output. Indicates regulation. Connect to an internal open drain 9 PGOOD N-MOSFET. 2.5V, 3.3V or 5V power supply. A ceramic decoupling capacitor with a value 10 VCNTL between 1 F and 4.7 F is required. Function Block Diagram EN VCNTL Control Thermal VIN REFIN Logic Protection + OCP Buffer SENSE - REFOUT VOUT - OP Driver + PGOOD + OCP Power - Good PGND GND www.richtek.com DS9040-03 July 2011 2