SH1107 128 X 128 Dot Matrix OLED/PLED Segment/Common Driver with Controller Features n Support maximum 128 X 128 dot matrix panel n Row re-mapping and column re-mapping n Embedded 128 X 128 bits SRAM n Vertical scrolling n Operating voltage: n On-chip oscillator - Logic voltage supply: VDD = 1.65V - 3.5V n Available internal DC-DC converter - DC-DC voltage supply: AVDD = 2.4V -3.5V n 256-step contrast control on monochrome passive OLED panel - OLED Operating voltage supply: Vpp=7.0V - 16.5V n Low power consumption n Maximum segment output current: 500A - Sleep mode: <5A n Maximum common sink current: 64mA n Wide range of operating temperatures: -40 to +85C n 8-bit 6800-series parallel interface, 8-bit 8080-series parallel interface, and 3-wire & 4-wire serial peripheral n Available in COG form. interface. 2 n 400KHz fast I C bus interface n Programmable frame frequency and multiplexing ratio General Description SH1107 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light emitting diode dot-matrix graphic display system. SH1107 consists of 128 segments, 128 commons that can support a maximum display resolution of 128 X 128. It is designed for Common Cathode type OLED panel. SH1107 embeds with contrast control, display RAM oscillator and efficient DC-DC converter, which reduces the number of external components and power consumption. SH1107 is suitable for a wide range of compact portable applications, such as sub-display of mobile phone, calculator and MP3 player, etc. 1 V2.1 SH1107 Block Diagram SEG0 SEG2...SEG126 COM0 ...COM127 SEG127... SEG3 SEG1 VDD VSS VCOMH Segment Common Segment VCL Power supply driver driver driver circuit VSL IREF Shift register Vpp Display data latch AVDD SW DC-DC SENSE FB 128*128 -dots VBREF Display Data RAM Output status selecor circuit Column address decoder Page Address Register 7-bit column address counter CL Display timing generator circuit 7-bit column address counter Bus Hoder Command Decoder Bus Hoder Oscillator CLS Microprocessor Interface I/O Buffer FRM IM0 IM1 IM2 D7 D6 D5 D4 D3 D2 D1 D0 CS RD RES A0 WR (SA0) (E) (R/W) (SI/SDA) (SCL) Figure 1 SH1107 Block Diagram 2 I/O buffer circuit line address decoder Line counter Initial display line register