TS13103-QFNR

LOAD VDD VGG WD SRC SUB VCC C VGG C SYS Regulator SYSP C PTO D SW1 C PTO REG SW1 V AC AD0 TS13103 AD1 C ISO SW2 CLK D SW2 C VCC C DATA SYSM C DATA C VDD C SUB VDD VGG WD SRC SUB Pin Description Pin Symbol Pin Function Description SYSP 1 Positive System Voltage Connect C to SYSM SYS SYSM 2 Negative System Voltage SUB 3 IC Substrate Bias Connect C Capacitor to SYSM SUB SRC 4 Switch Driver Supply Return Local common supply return 5 Internal Switch Driver Supply Connect Bypass Capacitor C to SRC VGG VGG SW2 6 Switch Output Node 2 7 Switch Output Node 2 SW2 DATA 8 Data Output AC Coupled Data Output CLK 9 Clock Input AC Coupled Clock Input WD 10 Watch Dog Control input for latching vs non-latching Switch VDD 11 Internal Supply 1 Connect Bypass Capacitor C to SYSM VDD AD0 12 Address Select 0 For logic 0, must be tied to SYSM on PCB For logic 1, must be tied to VDD on PCB AD1 13 Address Select 1 PTO 14 Power Transfer Output Connect to Power Transfer Capacitor C PTO SW1 15 Switch Output Node 1 SW1 16 Switch Output Node 1 PAD PAD Power PAD Must be floating or connected to SUB Functional Block Diagram PTO Power Management SYSP SW1 Over- Current AD0 AD1 Switch Digital Driver Control SW2 CLK Watchdog DATA SYSM Figure 1: TS13103 Block Diagram TS13103 2 of 16 Final Datasheet Rev 2.1 Semtech 28 July 2016 Proprietary & Confidential