XE1205I074TRLF

XE1205 XE1205 180 MHz 1GHz Low-Power, High Link Budget Integrated UHF Transceiver GENERAL DESCRIPTION KEY PRODUCT FEATURES The XE1205 is an integrated transceiver operating in Programmable RF output power: up to +15 dBm the 433, 868 and 915 MHz license-free ISM (Industrial, High Rx sensitivity: down to -121 dBm at 1.2 kbit/s, Scientific and Medical) frequency bands it can also -116 dBm at 4.8 kbits. address other frequency bands in the 180-1000 MHz Low power: RX=14 mA TX = 62 mA 15 dBm range. Its highly integrated architecture allows for Can accommodate 300-1000 MHz frequency range minimum external components while maintaining Wide band operation: up to 304.7 kbit/s, NRZ coding design flexibility. All major RF communication Narrow band operation: 25 kHz channels for data parameters are programmable and most of them can rates up to 4.8 kbit/s, NRZ coding optional be dynamically set. The XE1205 offers the unique transmitter pre-filtering to enable adjacent channel advantage of narrow-band and wide-band power below -37 dBm at 25 kHz communication, this without the need to modify the On-chip frequency synthesizer with minimum number or parameters of the external components. frequency resolution of 500 Hz The XE1205 is optimized for low power consumption Continuous phase 2-level FSK modulation while offering high RF output power and channelized Incoming data pattern recognition operation suited for both the European (ETSI EN 300- Built-in Bit-Synchronizer for incoming data and clock 220-1) and the North American (FCC part 15) synchronization and recovery regulatory standards. TrueRF technology enables a FEI (Frequency Error Indicator) with built-in AFC low-cost external component count (elimination of the RSSI (Received Signal Strength Indicator) SAW filter) whilst still satisfying ETSI and FCC 16-byte FIFO for transmit / receive data buffering regulations. and transfer via SPI bus APPLICATIONS ORDERING INFORMATION Narrow-band and wide-band security systems Part number Temperature range Package Voice and data over an RF link (1) XE1205I074TRLF -40 C to +85 C VQFN48 Process and building control (1) TR refers to tape & reel. Access control LF refers to Lead Free package. Home automation This device is WEEE and RoHS compliant Home appliances interconnection Rev 10 December 2008 www.semtech.com 1 XE1205 TABLE OF CONTENTS 1 Non-conformance ........................................................................................................................................................3 2 Functional Block Diagram...........................................................................................................................................3 3 Pin description.............................................................................................................................................................4 4 Electrical Characteristics............................................................................................................................................5 4.1 Absolute Maximum Operating Ranges ..........................................................................................................................5 4.2 Specifications.................................................................................................................................................................5 4.2.1 Operating Range ...........................................................................................................................................................5 4.2.2 Electrical Specifications .................................................................................................................................................5 5 Description...................................................................................................................................................................7 5.1 Data Operation Modes...................................................................................................................................................7 5.2 Receiver section ............................................................................................................................................................8 5.2.1 LNA & Receiver modes .................................................................................................................................................8 5.2.2 Interrupt signal mapping ................................................................................................................................................8 5.2.3 Receiver in continuous mode.........................................................................................................................................8 5.2.4 DATA pin in bidirectional or unidirectional mode (continuous mode only) ...................................................................14 5.2.5 Receiver in buffered mode...........................................................................................................................................14 5.2.6 Additional narrowband filter bandwidths ......................................................................................................................17 5.3 Transmitter section ......................................................................................................................................................18 5.3.1 Output power ...............................................................................................................................................................18 5.3.2 Transmitter in continuous mode...................................................................................................................................18 5.3.3 Transmitter in buffered mode.......................................................................................................................................20 5.4 Frequency synthesizer.................................................................................................................................................21 5.4.1 Clock Output for an external processor .......................................................................................................................21 6 Highest Bit RATES: example of 304.7 kbit/s operation ..........................................................................................22 6.1 Registers settings ........................................................................................................................................................22 6.1.1 Bitrate (BR) and frequency deviation (fdev).................................................................................................................22 6.1.2 Rx filter ........................................................................................................................................................................22 6.1.3 Tx filter.........................................................................................................................................................................22 6.2 Hardware settings........................................................................................................................................................23 6.3 Operation.....................................................................................................................................................................23 6.4 Typical performance ....................................................................................................................................................23 7 Serial interface definition and principle of operation .............................................................................................24 7.1 Serial Control Interface ................................................................................................................................................24 7.1.1 Chip configuration via SPI CONFIG interface.............................................................................................................25 7.1.2 Data transmission and reception via SPI DATA interface...........................................................................................26 7.2 Configuration and status registers ...............................................................................................................................28 7.2.1 Configuration register: general description ..................................................................................................................28 7.2.2 MCParam configuration register (main configuration parameters)...............................................................................29 7.2.3 IRQParam configuration register (IRQ parameters).....................................................................................................30 7.2.4 TXParam configuration register (transmitter configuration parameters) ......................................................................31 7.2.5 RXParam configuration register (receiver configuration parameters) ..........................................................................31 7.2.6 Pattern register ............................................................................................................................................................33 7.2.7 OSCParam configuration register (oscillator parameters) ...........................................................................................34 7.2.8 ADParam configuration register (additional settings)...................................................................................................35 7.3 Operating Modes .........................................................................................................................................................36 7.3.1 XE1205 switching time using SPI CONFIG interface..................................................................................................36 7.3.2 XE1205 switching time using SW(1:0) pins...............................................................................................................38 7.4 Selection of the reference frequency ...........................................................................................................................38 7.5 Clock output interface ..................................................................................................................................................39 7.6 Default settings at power-up ........................................................................................................................................39 7.7 Pad configuration versus chip modes ..........................................................................................................................40 8 Application information ............................................................................................................................................41 8.1 Matching network of the receiver.................................................................................................................................41 8.2 Matching network of the transmitter.............................................................................................................................41 8.3 VCO tank .....................................................................................................................................................................44 8.4 Loop filter of the frequency synthesizer .......................................................................................................................45 8.5 Reference crystal for the frequency synthesizer..........................................................................................................46 9 Packaging information ..............................................................................................................................................47 Semtech 2008 www.semtech.com 2