Product Information

CY2SSTV850ZC

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Datasheet
Zero Delay Buffer 10-Out Differential 48-Pin TSSOP

Manufacturer: Silicon Labs
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2: USD 4.0529 ea
Line Total: USD 8.1058

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MOQ: 2  Multiples: 1
Pack Size: 1
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Ships to you between Fri. 16 Jun to Thu. 22 Jun

MOQ : 1
Multiples : 1

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CY2SSTV850ZC
Silicon Labs

1 : USD 4.0529

0 - Global Stock


Ships to you between Fri. 16 Jun to Thu. 22 Jun

MOQ : 2
Multiples : 1

Stock Image

CY2SSTV850ZC
Silicon Labs

2 : USD 4.0529

     
Manufacturer
Silicon Labs
Product Category
Phase Locked Loops - PLL
Type
Clock Driver
Pin Count
48
Operating Temperature Classification
commercial
Operating Temp Range
0 C To 70 C
Rad Hardened
No
Pll Input Freq Max
170(Mhz)
Programmable
No
Number Of Elements
1
Operating Supply Voltage Min
2.375 V
Operating Supply Voltage Typ
2.5 V
Operating Supply Voltage Max
2.625 V
Package Type
TSSOP
Pll Input Freq Min
60(Mhz)
Supply Current
12 mA
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CY2SSTV850 Differential Clock Buffer/Driver Features Description Phase-locked loop clock distribution for Double Data This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD Rate Synchronous DRAM applications operation and differential data input and output levels. 1:10 differential outputs This device is a zero-delay buffer that distributes a differential clock input pair (CLKINT, CLKINC) to ten differential pair of External Feedback pins (FBINT, FBINC) are used to clock outputs (YT[0:9], YC[0:9]) and one differential pair synchronize the outputs to the clock input feedback clock output (FBOUTT, FBOUTC). The clock outputs SSCG: Spread Aware for EMI reduction are individually controlled by the serial inputs SCLK and SDATA. 48-pin SSOP and TSSOP packages The two-line serial bus can set each output clock pair (YT[0:9], Conforms to JEDEC JC40 and JC42.5 DDR YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL specifications is turned off and bypassed for test purposes. The PLL in this device uses the input clocks (CLKINT,CLKINC) and the feedback clocks (FBINT,FBINC) to provide high-performance, low-skew, low-jitter output differential clocks. Block Diagram Pin Configuration 10 VSS 1 48 VSS YT0 YC0 YC0 2 47 YC5 YT1 3 46 YT5 YT0 YC1 4 45 VDDQ VDDQ YT1 5 44 YT6 YT2 YC2 YC1 6 43 YC6 VSS 7 42 VSS YT3 VSS 8 41 VSS YC3 SCLK Serial 9 40 YC7 Interface YC2 YT4 Logic SDATA 10 39 YT7 YT2 YC4 VDD 11 38 VDDQ YT5 SCLK 12 37 SDATA YC5 CLKINT 13 36 FBINT YT6 14 35 FBINC CLKINC YC6 15 34 VDDQ VDDI CLKINT YT7 16 33 FBOUTC AVDD CLKINC YC7 FBOUTT AVSS 17 32 PLL YT8 FBINT VSS 18 31 VSS YC8 FBINC YC3 19 30 YC8 20 29 YT8 YT9 YT3 YC9 21 28 VDDQ VDDQ 22 27 YT9 YT4 AVDD YC4 23 26 YC9 FBOUTT FBOUTC VSS 24 25 VSS ......................... Document #: 38-07457 Rev. *A Page 1 of 9 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com CY2SSTV850 CY2SSTV850 [1, 2] Pin Description Pin Name I/O Description Electrical Characteristics 13 CLKINT I Complementary Clock Input. LV Differential Input 14 CLKINC I Complementary Clock Input. 35 FBINC I Feedback Clock Input. Connect to FBOUTC for Differential Input accessing the PLL. 36 FBINT I Feedback Clock Input. Connect to FBOUTT for accessing the PLL. 3, 5, 10, 20, 22 YT(0:9) O Clock Outputs Differential Outputs 46, 44, 39, 29,27 2, 6, 9, 19, 23 YC(0:9) O Clock Outputs 47, 43, 40,30,26 32 FBOUTT O Feedback Clock Output. Connect to FBINT for Differential Outputs normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 33 FBOUTC O Feedback Clock Output. Connect to FBINC for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 12 SCLK I, PU Serial Clock Input. Clocks data at SDATA into Data Input for the two-line serial the internal register. bus 37 SDATA I/O, PU Serial Data Input. Input data is clocked to the Data Input and Output for the internal register to enable/disable individual two-line serial bus outputs. This provides flexibility in power management. 11 VDD 2.5V power Supply for Logic 2.5V Nominal 4, 21, 28, 34, 38, 45 VDDQ 2.5V Power Supply for Output Clock Buffers 2.5V Nominal 16 AVDD 2.5V Power Supply for PLL 2.5V Nominal 15 VDDI Power Supply for two-line serial Interface 2.5V or 3.3V Nominal 1, 7, 8, 18, 24, 25, VSS Common Ground 0.0V Ground 31, 41, 42, 48 17 AVSS Analog Ground 0.0V Analog Ground Notes: 1. PU= internal pull-up 2. A bypass capacitor (0.1 F) should be placed as close as possible to each positive power pin (<0.2). If these bypass capacitors are not close to the pins their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces .........................Document #: 38-07457 Rev. *A Page 2 of 9

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

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