Si53154 PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 QUAD FANOUT BUFFER Features PCI-Express Gen 1, Gen 2, Gen 3, Four PCI-Express buffered clock and Gen 4 common clock outputs compliant Clock input spread tolerable Supports Serial ATA (SATA) at Supports LVDS outputs 100 MHz 2 I C support with readback 100210 MHz operation capabilities Low power, push pull, differential Extended temperature: output buffers 40 to 85 C Internal termination for maximum 3.3 V power supply integration 24-pin QFN package Dedicated output enable pin for Ordering Information: each output See page 17. Applications Pin Assignments Network attached storage Wireless access point Multi-function printers Routers 24 23 22 21 20 19 Description VDD 1 18 OE3* VDD The Si53154 is a spread spectrum tolerant PCIe clock buffer that can source 17 OE1* 2 four PCIe clocks simultaneously. The device has four hardware output enable VDD 16 3 DIFF3 25 GND DIFF3 15 control inputs for enabling the respective differential outputs on the fly. The VSS 4 2 2 14 DIFF2 device also features output enable control through I C communication. I C OE2* 5 13 DIFF2 programmability is also available to dynamically control skew, edge rate and VDD 6 amplitude on the true, compliment, or both differential signals on the clock 7 8 9 10 11 12 outputs. This control feature enables optimal signal integrity as well as optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is *Note: Internal 100 kohm pull-up. quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. Patents pending Functional Block Diagram DIFF0 DIFF1 DIFFIN DIFFIN DIFF2 DIFF3 Control & Memory SCLK SDATA Control RAM OE 3:0 Rev. 1.3 4/16 Copyright 2016 by Silicon Laboratories Si53154 VSS OE0* DIFFIN DIFF0 DIFFIN DIFF0 VDD DIFF1 SDATA DIFF1 SCLK VDDSi53154 2 Rev. 1.3