Si5330 1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or Output-output skew: 100 ps differential input clock signals Propagation delay: 2.5 ns typ Generates four differential Single core supply with excellent (LVPECL, LVDS, HCSL) or eight PSRR: 1.8, 2.5, or 3.3 V single-ended (CMOS, SSTL, Output driver supply voltage HSTL) outputs independent of core supply: 1.5, Provides signal level translation 1.8, 2.5, or 3.3 V Differential to single-ended Loss of Signal (LOS) indicator Ordering Information: Single-ended to differential allows system clock monitoring See page 14. Differential to differential Output Enable (OEB) pin allows Single-ended to single-ended glitchless control of output clocks Wide frequency range Low power: 10 mA typical core Pin Assignments LVPECL, LVDS: 5 to 710 MHz current HCSL: 5 to 250 MHz Industrial temperature range: SSTL, HSTL: 5 to 350 MHz 40 to +85 C CMOS: 5 to 200 MHz Small size: 24-lead, 4 x 4 mm Additive jitter: 150 fs RMS typ QFN Applications High Speed Clock Distribution PCI Express 2.0/3.0 Ethernet Switch/Router Fibre Channel SONET / SDH MSAN/DSLAM/PON Telecom Line Cards Functional Block Diagram Rev. 1.2 4/17 Copyright 2017 by Silicon Laboratories Si5330 Si5330 * Functional Block Diagrams Based on Orderable Part Number Figure 1. Si5330 Functional Block Diagrams *Note: See Table 11 for detailed ordering information. 2 Rev. 1.2