1 2 3 4 5 6
Si5330
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW
CLOCK BUFFER/LEVEL TRANSLATOR
Features
Supports single-ended or Output-output skew: 100 ps
differential input clock signals
Propagation delay: 2.5 ns typ
Generates four differential
Single core supply with excellent
(LVPECL, LVDS, HCSL) or eight
PSRR: 1.8, 2.5, or 3.3 V
single-ended (CMOS, SSTL,
Output driver supply voltage
HSTL) outputs
independent of core supply: 1.5,
Provides signal level translation
1.8, 2.5, or 3.3 V
Differential to single-ended
Loss of Signal (LOS) indicator
Ordering Information:
Single-ended to differential
allows system clock monitoring
See page 14.
Differential to differential
Output Enable (OEB) pin allows
Single-ended to single-ended
glitchless control of output clocks
Wide frequency range
Low power: 10 mA typical core
Pin Assignments
LVPECL, LVDS: 5 to 710 MHz current
HCSL: 5 to 250 MHz
Industrial temperature range:
SSTL, HSTL: 5 to 350 MHz
40 to +85 C
CMOS: 5 to 200 MHz
Small size: 24-lead, 4 x 4 mm
24 23 22 21 20 19
Additive jitter: 150 fs RMS typ
QFN
CLK1A
IN1
CLK1B
IN2
Applications
IN3 VDDO1
GND
High Speed Clock Distribution PCI Express 2.0/3.0 GND
RSVD_GND
VDDO2
Ethernet Switch/Router Fibre Channel
RSVD_GND
CLK2A
SONET / SDH MSAN/DSLAM/PON
RSVD_GND CLK2B
Telecom Line Cards
7 8 9 10 11 12
Functional Block Diagram
V
DD
V
DDO0
Si5330
CLK0
V
DDO1
CLK1
Single-ended Single-ended
IN
or V or
DDO2
Differential Differential
CLK2
V
DDO3
LOS
CLK3
Control
OEB
Rev. 1.0 4/12 Copyright 2012 by Silicon Laboratories Si5330
VDD
VDD
LOS RSVD_GND
CLK3B CLK0A
CLK3A
CLK0B
VDDO3
VDDO0
RSVD_GND
OEB
13 14 15 16 17 18Si5330
*
1. Functional Block Diagrams Based on Orderable Part Number
1:8 Single-Ended to Single-Ended Buffer
1:4 Differential to Differential Buffer
V
DDO0 V
DDO0
Si5330A/B/C
Si5330F
CLK0A
CLK0A
CLK0B
CLK0B
V
IN1 DDO1 V
DDO1
CLK1A IN3
CLK1A
IN2
CLK1B
CLK1B
IN1
V
IN3 DDO2 V
DDO2
IN2
CLK2A
CLK2A
CLK2B
CLK2B
LOS
LOS
Control V
DDO3 Control V
DDO3
OEB
OEB
CLK3A
CLK3A
CLK3B
CLK3B
1:4 Single-Ended to Differential Buffer
1:8 Differential to Single-Ended Buffer
V
DDO0
V
DDO0 Si5330K/L/M
Si5330G/H/J
CLK0A
CLK0A
CLK0B
CLK0B
V
DDO1
V
IN1 DDO1
IN3
CLK1A
CLK1A
IN2
CLK1B
CLK1B
IN1
V
DDO2
V
IN3 DDO2
IN2
CLK2A
CLK2A
CLK2B
CLK2B
LOS
LOS
V
Control DDO3
V
Control DDO3
OEB
OEB
CLK3A
CLK3A
CLK3B
CLK3B
Figure 1. Si5330 Functional Block Diagrams
*Note: See Table 11 for detailed ordering information.
2 Rev. 1.0