34 35 36 37 38 39 40 41 42 43 44 Si53312 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX (<1.25 GHZ) Features 10 differential or 20 LVCMOS outputs Low output-output skew: <70 ps Ultra-low additive jitter: 45 fs rms Low propagation delay variation: <400 ps Wide frequency range: dc to 1.25 GHz Independent V and V : DD DDO Any-format input with pin selectable 1.8/2.5/3.3 V output formats: LVPECL, Low Power Excellent power supply noise LVPECL, LVDS, CML, HCSL, rejection (PSRR) LVCMOS Selectable LVCMOS drive strength to 2:1 mux with hot-swappable inputs tailor jitter and EMI performance Asynchronous output enable Small size: 44-QFN (7 mm x 7 mm) Output clock division: /1, /2, /4 RoHS compliant, Pb-free Ordering Information: (/2 and /4 for dc to 725 MHz) Industrial temperature range: See page 28. 40 to +85 C Applications Pin Assignments High-speed clock distribution Storage Ethernet switch/router Telecom Si53312 Optical Transport Network (OTN) Industrial SONET/SDH Servers PCI Express Gen 1/2/3 Backplane clock distribution 1 DIVA 33 DIVB 2 32 SFOUTA 1 SFOUTB 1 Description SFOUTA 0 3 31 SFOUTB 0 4 30 Q2 Q7 5 29 Q2 Q7 GND 6 The Si53312 is an ultra low jitter ten output differential buffer with pin-selectable GND 28 NC PAD 7 27 Q1 Q8 output clock signal format and divider selection. The Si53312 features a 2:1 mux, 8 26 Q1 Q8 9 25 Q0 Q9 making it ideal for redundant clocking applications. The Si53312 utilizes Skyworks 10 24 Q0 Q9 Solutions advanced CMOS technology to fanout clocks from dc to 1.25 GHz with 11 23 NC CLK SEL guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53312 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry. Patents pending Functional Block Diagram Power Vref V Supply REF DIVA Generator Filtering VDDOA SFOUTA 1:0 OEA Q0, Q1, Q2, Q3, Q4 DivA Q0, Q1, Q2, Q3, Q4 CLK0 /CLK0 DIVB VDDOB CLK1 SFOUTB 1:0 OEB /CLK1 Q5, Q6, Q7, Q8, Q9 DivB Switching Q5, Q6, Q7, Q8, Q9 CLK SEL Logic Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 3, 2021 VDD 12 VDDOA 13 NC Q3 14 CLK0 Q3 15 CLK0 Q4 16 OEA Q4 V 17 REF GND OEB 18 Q5 19 CLK1 Q5 20 CLK1 Q6 21 Q6 NC 22 GND VDDOBSi53312 TABLE OF CONTENTS Section Page 1. Electrical Specifications .3 2. Functional Description .11 2.1. Universal, Any-Format Input .11 2.2. Input Bias Resistors .13 2.3. Voltage Reference (VREF) 13 2.4. Universal, Any-Format Output Buffer 14 2.5. Input Mux and Output Enable Logic .15 2.6. Flexible Output Divider .15 2.7. Power Supply (V and V ) 15 DD DDOX 2.8. Output Clock Termination Options 16 2.9. AC Timing Waveforms .19 2.10. AC Timing Waveforms 20 2.11. Typical Phase Noise Performance .21 2.12. Input Mux Noise Isolation 24 2.13. Power Supply Noise Rejection 24 3. Pin Description: 44-Pin QFN .25 4. Ordering Guide 28 5. Package Outline .29 5.1. 7x7 mm 44-QFN Package Diagram .29 6. PCB Land Pattern 30 6.1. 7x7 mm 44-QFN Package Land Pattern 30 7. Top Marking 31 7.1. Si53312 Top Marking 31 7.2. Top Marking Explanation .31 Document Change List .32 Contact Information 33 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 3, 2021