SI8451BA-B-IS1 Silicon Labs

Si8450/51/52/55 LOW POWER FIVE-CHANNEL DIGITAL ISOLATOR Features High-speed operation Up to 2500 V isolation RMS DC to 150 Mbps 60-year life at rated working No start-up initialization required voltage Wide Operating Supply Voltage: Precise timing (typical) 2.705.5 V <10 ns worst case Ultra-low-power (typical) 1.5 ns pulse width distortion 5 V Operation: 0.5 ns channel-channel skew < 1.6 mA per channel at 1 Mbps 2 ns propagation delay skew < 6 mA per channel at 100 Mbps 6 ns minimum pulse width 2.70 V Operation: Transient Immunity 25 kV/s Ordering Information: < 1.4 mA per channel at 1 Mbps Wide temperature range See page 28. < 4 mA per channel at 100 Mbps 40 to 125 C at 150 Mbps High electromagnetic immunity RoHS-compliant packages SOIC-16 narrow body Applications Industrial automation systems Isolated ADC, DAC Hybrid electric vehicles Motor control Isolated switch mode supplies Power inverters Communications systems Safety Regulatory Approvals UL 1577 recognized VDE certification conformity Up to 2500 V for 1 minute IEC 60747-5-2 RMS (VDE0884 Part 2) CSA component notice 5A approval IEC 60950-1, 61010-1 (reinforced insulation) Description Silicon Lab s family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages when compared to legacy isolation technologies. The operating parameters of these products remain stable across wide temperature ranges throughout their service life. For ease of design, only VDD bypass capacitors are required. Data rates up to 150 Mbps are supported, and all devices achieve worst-case propagation delays of less than 10 ns. All products are safety certified by UL, CSA, and VDE and support withstand voltages of up to 2.5 kVrms. These devices are available in a 16-pin narrow- body SOIC package. Rev. 1.6 4/18 Copyright 2018 by Silicon Laboratories Si8450/51/52/55 Not Recommended for New DesignsSi8450/51/52/55 TABLE OF CONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.1. Enable Pin Causes Outputs to Go Low (Revision A Only) . . . . . . . . . . . . . . . . . . . .25 3.2. Power Supply Bypass Capacitors (Revision A and Revision B) . . . . . . . . . . . . . . . .25 3.3. Latch Up Immunity (Revision A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4. Pin Descriptions (Si8450/51/52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 5. Pin Descriptions (Si8455) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 7. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 8. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 9. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 9.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Rev. 1.6 2 Not Recommended for New Designs