SL18861DI 3-Channel Clock Distribution Buffer Key Features Description The SL18861DI product is a high performance 3 output Low current consumption: - 2.7mA-typ (VDD=1.8V, CL=0) clock distribution buffer and provides 3 outputs from a single input clock by using SLI proprietary low phase 1.70V to 3.65V power supply operation noise and low power dissipation circuit design. 10MHz to 52MHz CLKIN range Supports LVCMOS or Sine Inputs The SL18861DI can be used in baseband mobile RF Supports 3 single-ended LVCMOS square wave or applications including WLAN, Bluetooth and DVB-H as an clipped sine wave outputs input clock reference. The product designed to isolate OE1/2/3 functions for each CLKOUT1/2/3 outputs each device driven by their clock outputs to minimize OE OSC control pin to enable external TCXO/XO interference between these devices. Ultra-Low phase noise Each of the clock buffer outputs can be individually Ultra low standby current disabled by using OE1/2/3 control pins to reduce the 10-pin TDFN package (1.4x2.0x0.75 mm) power consumption if the connected device does not need Industrial -40 C to 85 C temperature range the clock. The device operates from single power supply from 1.70V to 3.65V and from -40 C to 85 C. Application Benefits Fast Time-to-market Smart Mobile Handsets Cost Reduction Multi-mode RF Clock Distribution Low Power Dissipation Baseband Peripheral Clock Distribution Low Phase Noise Block Diagram 8 CLKOUT1 3 9 CLKOUT2 CLKIN OE OSC 4 10 CLKOUT3 CONTROL LOGIC 6 7 5 2 1 OE1 OE2 OE3 VDD VSS Rev 1.2, December 21 , 2010 Page 1 of 12 2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com SL18861DI Pin Configuration VSS 1 10 CLKOUT3 2 9 CLKOUT2 VDD CLKOUT1 3 8 CLKIN OE OSC 4 7 OE2 OE3 5 6 OE1 10-Pin TDFN Package Pinout Pin Description Pin Pin Name Pin Type Pin Description Number 1 VSS Power Power supply ground. 2 VDD Power 2.25 to 3.65V or 1.8V +/-5% positive power supply 3 CLKIN Input External clock input pin. VSS to VDD CMOS level. 4 OE OSC Output Crystal oscillator enable pin. If OE1=OE2=OE3=0 then OE OSC=0. OE OSC=1 for all the other OE1/2/3 logic states. 5 OE3 Input Output enable pin for CLKOUT3. The input has 150k -typ on-chip pull- down resistor. 6 OE1 Input Output enable pin for CLKOUT1. The input has 150k -typ on-chip pull- down resistor. 7 OE2 Input Output enable pin for CLKOUT2. The input has 150k -typ on-chip pull- down resistor. 8 CLKOUT1 Output Clock output-1. Clock frequency is the same as CLKIN. 9 CLKOUT2 Output Clock output-2. Clock frequency is the same as CLKIN. 10 CLKOUT3 Output Clock output-3. Clock frequency is the same as CLKIN. OE1 OE2 OE3 OE OSC CLKOUT1 CLKOUT2 CLKOUT3 (Input) (Input) (Input) (Output) 0 0 0 0 Hi-Z Hi-Z Hi-Z 1 0 0 1 CLOCK Hi-Z Hi-Z 1 1 0 1 CLOCK CLOCK Hi-Z 1 1 1 1 CLOCK CLOCK CLOCK Table 1. Truth Table for OE1/2/3, OE OSC and CLKOUT1/2/3 Rev 1.2, December 21 , 2010 Page 2 of 12