SL23EP04 Not Recommended for New Designs Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB) Key Features Description 10 to 220 MHz operating frequency range The SL23EP04 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to four Low output clock skew: 60ps-typ (4) clock outputs from one (1) reference input clock, for Low output clock Jitter: high speed clock distribution applications. Low part-to-part output skew: 150 ps-typ The product has an on-chip PLL and a feedback pin 3.3V to 2.5V power supply range (FBK) which can be used to obtain feedback from any one of the 4 output clocks. The SL23EP04 offers X/2,1X Low power dissipation: and 2X frequency options at the output with respect to - 12 mA-typ at 66MHz and VDD=3.3V input reference clock. Refer to the Product Configuration - 10 mA-typ at 66MHz and VDD=2.5V Table for the details of these options. One input drives 4 outputs The SL23EP04-1H and -2H High Drive version operates Multiple configurations and drive options up to 220 MHz and 200MHz at 3.3 and 2.5V power supplies respectively. The standard versions -1 and -2 SpreadThru PLL that allows use of SSCG operate up to 167MHz and 135MHz at 3.3V and 2.5V Available in 8-pin SOIC package power supplies respectively with CL=15pF output load. Available in Commercial and Industrial grades The SL23EP04 enter into Power Down (PD) mode if the Applications input at CLKIN is DC (GND to VDD). In this state all 4 output clocks are tri-stated and the PLL is turned off, Printers, MFPs and Digital Copiers leading to 8A-typ power supply current draw. PCs and Work Stations Routers, Switchers and Servers Benefits Datacom and Telecom Up to four (4) distribution of input clock High-Speed Digital Embeded Systems Standard and High-Drive levels to control impedance level, frequency range and EMI Low skew, jitter and power dissipation Block Diagram FBK Low Power and Low Jitter CLKA1 PLL CLKIN CLKA2 (Divider for -2 only) /2 CLKB1 CLKB2 VDD GND Rev 2.1, May 15, 2008 Page 1 of 15 2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com Not Recommended for New Designs SL23EP04 Pin Configuration CLKIN 1 8 FBK 2 CLKA1 7 VDD 3 6 CLKA2 CLKB2 GND 4 5 CLKB1 8-Pin SOIC Pin Description Pin Pin Name Pin Type Pin Description Number 1 CLKIN Input Reference Frequency Clock Input. Weak pull-down (250k). 2 CLKA1 Output Buffered Clock Output Weak pull-down (250k). 3 CLKA2 Output Buffered Clock Output. Weak pull-down (250k). 4 GND Power Power Ground. 5 CLKB1 Output Buffered Clock Output. Weak pull-down (250k). 6 CLKB2 Output Buffered Clock Output. Weak pull-down (250k). 7 VDD Power 2.5V to 3.3V Power Supply. 8 FBK Input PLL Feedback Input. This pin must be connected to one of the clock outputs. May 15, 2008 Page 2 of 15 Not Recommended for New Designs