SL23EP05 Not Recommended for New Designs LOW JITTER AND SKEW 10 TO 220 MHZ ZERO DELAY BUFFER (ZDB) Features 10 to 220 MHz operating Low power dissipation: frequency range 16 mA-max at 66 MHz and VDD = 3.3 V Low output clock jitter: 14 mA-max at 66 MHz and 50 ps-typ cycle-to-cycle jitter VDD = 2.5 V 20 ps-typ period jitter One input drives five outputs Low output-to-output skew: organized as 4+1 30 ps-typ SpreadThru PLL that allows Low product-to-product skew: use of SSCG 60 ps-typ Standard and High-Drive options Wide 2.5 V to 3.3 V power supply Available in 8 pin SOIC and range TSSOP packages Ordering Information: Available in Commercial and See page 14. Industrial grades Applications Pin Assignments Printers and MFPs Routers, Switchers and Servers Digital Copiers Digital Embedded Systems SL23EP05 PCs and Work Stations Benefits Up to five distribution of input Low power dissipation, jitter and clock skew Standard and High-Drive levels Low cost to control impedance level, frequency range and EMI Description Patents pending The SL23EP05 is a low skew, low jitter, and low power Zero Delay Buffer (ZDB) designed to produce up to five clock outputs from one reference input clock for high speed clock distribution applications. The product has an on- chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL23EP05 is available with two drive strength versions called 1 and 1H. The 1 is the standard-drive version and 1H is the high-drive version. The SL23EP05 high-drive version operates up to 220 MHz and 180 MHz at 3.3 V and 2.5 V power supplies, respectively. The standard drive version 1 operates up to 200 MHz and 167 MHz at 3.3 V and 2.5 V, respectively. The SL23EP05 enter into Power Down (PD) mode if the input at CLKIN is less then 2.0 MHz or there is no rising edge. In this state all five outputs are tri-stated and the PLL is turned off leading to less than 10 A of power supply current draw. Rev. 2.2 5/15 Copyright 2015 by Silicon Laboratories SL23EP05 Not Recommended for New DesignsSL23EP05 Functional Block Diagram 2 Rev. 2.2 Not Recommended for New Designs