74VHC594 8 BIT SHIFT REGISTER WITH OUTPUT REGISTER HIGH SPEED: t = 4.2ns (TYP.) at V = 5V PD CC LOW POWER DISSIPATION: I = 4 A (MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28% V (MIN.) NIH NIL CC POWER DOWN PROTECTION ON INPUTS SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 8 mA (MIN) OH OL Table 1: Order Codes BALANCED PROPAGATION DELAYS: t t PLH PHL PACKAGE T & R OPERATING VOLTAGE RANGE: SOP M74VHC594RMTR V (OPR) = 2V to 5.5V CC TSSOP M74VHC594TTR PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 594 A serial (QH) output is provided for cascading IMPROVED LATCH-UP IMMUNITY purposes. Both the shift register and storage LOW NOISE: V = 0.8V (MAX.) OLP register use positive-edge triggered clocks. If the clocks are connected together, the shift register DESCRIPTION state will always be one clock pulse ahead of the The 74VHC594 is an high speed CMOS 8-BIT storage register. SHIFT REGISTERS fabricated with sub-micron Power down protection is provided on all inputs 2 silicon gate C MOS technology. and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage used to interface 5V to 3V. register. Separate clocks and direct overriding All inputs are equipped with protection circuits clear (SCLR, RCLR) are provided for both the shift against static discharge, giving them 2KV ESD register and the storage register. immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols Rev. 5 November 2004 1/1474VHC594 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N SYMBOL NAME AND FUNCTION 1, 2, 3, 4, 5, QA to QH Data Outputs 6, 7, 15 9 QH Serial Data Output 10 SCLR Shift Register Clear Input 11 SCK Shift Register Clock Input 13 RCLR Storage Register Clear Input 14 SI Serial Data Input 12 RCK Storage Register Clock Input 8 GND Ground (0V) 16 V Positive Supply Voltage CC Table 3: Truth Table INPUTS OUTPUTS SI SCK SCLR RCK RCLR X X L X X SHIFT REGISTER IS CLEAR FIRST STAGE OF SHIFT REGISTER GOES LOW LHXX OTHER STAGES STORE THE DATA OF PREVI- OUS STAGE, RESPECTIVELY FIRST STAGE OF SHIFT REGISTER GOES HIGH OTHER STAGES STORE THE DATA OF PREVI- HHXX OUS STAGE, RESPECTIVELY L H X X SHIFT REGISTER STATE IS NOT CHANGED X X X X L STORAGE REGISTER IS CLEARED SHIFT REGISTER DATA IS STORED IN THE XX X H STORAGE REGISTER X X X H STORAGE REGISTER STATE IS NOT CHANGED X: Dont Care 2/14