CLT01-38SQ7-TR

CLT01-38SQ7 Datasheet High speed digital input current limiter 37 48 36 1 Features 8 inputs - 8-bit SPI output High side input with common ground 5 V voltage regulator 12 25 24 13 Bottom view Package: QFN 7x7 - 48L 48 47 46 45 44 43 42 41 40 39 38 37 35 V reverse polarity capable 1 36 2 35 3 34 4 33 Adjustable current limiters 5 32 6 31 7 30 LED output for visual status 8 29 9 28 10 27 Optional: 16-bit mode with parity check, temperature and voltage alarms 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 Daisy chain capable Top view 37 48 Input digital filter with adjustable delay: 20 s to 3 ms 36 1 Power dissipation: 78 mW per channel Complies with the following standards: IEC 61000-4-2: 8 kV (contact discharge), 15 kV (air discharge) 25 12 24 13 IEC 61000-4-4: 4 kV Bottom view 48 47 46 45 44 43 42 41 40 39 38 37 1 36 IEC 61000-4-5: Input: 1 kV, power supply: 2.5 kV 2 35 3 34 4 33 5 32 6 31 7 30 29 8 9 28 Applications 10 27 26 11 12 25 13 14 15 16 17 18 19 20 21 22 23 24 Programmable logic controller and remote input modules Top view High speed protected termination for digital input with serialized SPI output IEC61131-2 type 1, 2 and 3 Product status link Compliant with EN60947-5-2 CLT01-38SQ7 Benefits Simplified design due to Built-in over voltage robustness and immune data transfer Compliance with sensors and PLC s standards Space saving in cost effective solution with Integrated QFN 7x7 package SPI output reducing opto-couplers quantity Energy efficient solution Energy-less input LED visual status powered by inputs current Low overall dissipation versus discrete Description The CLT01-38SQ7 provides an 8-line protected digital input termination with serialized state transfer. This device enhances the I/O module density by cutting the dissipation (78 mW per input) and reducing the count of opto-transistors. Its 6.25 MHz SPI peripheral output serializes the input state transfer to the I/O module controller. DS11183 - Rev 2 - November 2021 www.st.com For further information contact your local STMicroelectronics sales office.CLT01-38SQ7 Circuit block diagrams 1 Circuit block diagrams Figure 1. Circuit block diagram V DD VV IN Protected input 1 DDDD MISOMISO V R /MIS/MISOO LD 1 V <V IN R 8 lines 8 lines COMCOM S VVDDDD WRITE COM P SHIFT MOSIMOSI CAPTURE SCSCKK IN I /CS/CS MOSI SHIFT 7 lines LD SPMSPM I 16-bit 4 lines VV CC Power Power REF Current reset supply reference V DVR DD VV CSCS Under voltage OSC Over temperature 8 / 64 Oscillator Clock divider alarm alarm Figure 2. Basic application schematic ACPL-K73L ACPL-W70L V DD2 V LED6 DD DVR LED7 R OSC OSC LED8 SPM COM P COM P R PD V V V V V V V V V CC I1 I2 I3 I4 I5 I6 I7 I8 DS11183 - Rev 2 page 2/16 Protected input I = 2 t o 8 R C V C /CS R S V CS SCK COM MOSI 16 s / 3 ms digital filters P R I IN1 R I IN2 MISO Parity 8 lines Input state register R I COM bits gen. IN3 S R R I REF IN4 REF COM P LED1 Control state register Data state register R I IN5 LED2 R I IN6 LED3 R I IN7 LED4 Transfer logic R I LED5 IN8