L6717TR STMicroelectronics

L6717 High-efficiency hybrid AM2r2 controller 2 with I C interface and embedded drivers Features Hybrid controller for both PVI and SVI CPUs Dual controller with 2 embedded high current drivers + 2 PWM for external driver for CPU CORE and 1 embedded high current driver for CPU NB VFQFPN48 Dynamic phase management (DPM) VFQFPN48 2 I C interface to control offset, switching frequency and power management options Description Dual-edge asynchronous architecture with LTB technology L6717 is a hybrid CPU power supply controller embedding 2 high-current drivers for the CORE PSI management to increase efficiency in light- section and 1 driver for the NB section - requiring load conditions up to 2 external drivers when the CORE section Dual overcurrent protection: Total and per- works at 4 phase to optimize the application over- phase all cost. Accurate voltage positioning 2 I C interface allows to manage offset both CORE Dual remote sense and NB sections, switching frequency and dynamic phase management saving in Feedback disconnection protection component count, space and power consumption. Programmable OV protection Dynamic phase management automatically Oscillator internally fixed at 200 kHz externally adjusts phase-count according to CPU load adjustable optimizing the system efficiency under all load LSLess startup to manage pre-biased output conditions. VFQFPN48 Package The dual-edge asynchronous architecture is optimized by LTB technology allowing fast load- Applications transient response minimizing the output capacitor and reducing the total BOM cost. Hybrid high-current VRM / VRD for desktop / Server / Workstation / IPC CPUs supporting Fast protection against load over current is PVI and SVI interface provided for both the sections. Feedback disconnection protection prevents from damaging High-density DC / DC converters the load in case of disconnections in the system board. L6717 is available in VFQFPN48 package. Table 1. Device summary Order codes Package Packing L6717 Tray VFQFPN48 L6717TR Tape and reel March 2010 Doc ID 17326 Rev 1 1/56 www.st.com 56 Obsolete Product(s) - Obsolete Product(s)Contents L6717 Contents 1 Typical application circuit and block diagram 4 1.1 Application circuit 4 1.2 Block diagram . 7 2 Pins description and connection diagrams 8 2.1 Pin descriptions . 8 2.2 Thermal data 13 3 Electrical specifications . 14 3.1 Absolute maximum ratings 14 3.2 Electrical characteristics 15 4 Device description and operation . 18 5 Hybrid CPU support and CPU TYPE detection 19 5.1 PVI - parallel interface . 19 5.2 PVI start-up . 19 5.3 SVI - serial interface . 21 5.4 SVI start-up . 21 5.4.1 Set VID command . 21 5.4.2 PWROK de-assertion 24 5.4.3 PSI L and efficiency optimization at light-load . 24 5.4.4 HiZ management 25 5.4.5 Hardware jumper override - V FIX 25 6 Power manager I2C . 26 6.1 Power manager commands . 26 6.1.1 Overspeeding command (OVRSPD) . 29 6.1.2 Overvoltage threshold adjustment (OV SET) 30 6.1.3 Switching frequency adjustment (FSW ADJ) 30 6.1.4 Droop function adjustment (DRP ADJ) . 31 6.1.5 Power management flags . 31 6.2 Dynamic phase management (DPM) 32 2/56 Doc ID 17326 Rev 1 Obsolete Product(s) - Obsolete Product(s)