M34F04-WMN6TP STMicroelectronics

M34F04 2 4-Kbit serial I C bus EEPROM with write control of the top half of memory Datasheet production data Features 2 Two-wire I C serial interface supports 400 kHz protocol Single supply voltage 2.5 to 5.5 V Write control of the top half of memory (addresses 100h to 1FFh) Byte and Page Write (up to 16 Bytes) SO8 (MN) Random and Sequential Read modes 150 mil width Self-timed programming cycle Automatic address incrementing Enhanced ESD/latch-up behavior More than 1 million erase/write cycles More than 40 year data retention Package SO8 ECOPACK 2 May 2015 DocID11090 Rev 4 1/26 This is information on a product in full production. www.st.comContents M34F04 Contents 1 Description . 6 2 Signal description . 8 2.1 Serial clock (SCL) 8 2.2 Serial data (SDA) 8 2.3 Chip enable (E1, E2) . 8 2.4 Write control (WC) . 8 2.5 Supply voltage (V ) . 9 CC 2.5.1 Operating supply voltage V CC 9 2.5.2 Internal device reset 9 2.5.3 Power-down . 9 3 Device operation . 10 3.1 Start condition 10 3.2 Stop condition 10 3.3 Acknowledge bit (ACK) 10 3.4 Data input . 10 3.5 Memory addressing 11 3.6 Write operations 12 3.7 Byte write . 12 3.8 Page write 13 3.9 Minimizing system delays by polling on ACK 14 3.10 Read operations 15 3.11 Random address read . 15 3.12 Current address read 16 3.13 Sequential read 16 3.14 Acknowledge in read mode . 16 4 Initial delivery state . 17 5 Maximum ratings . 18 6 DC and AC parameters 19 2/26 DocID11090 Rev 4