SPC582B60E1MH00Y STMicroelectronics

SPC582Bx SPC58 2B Line - 32 bit Power Architecture automotive MCU Single core 80Mhz, 1MByte Flash, ASIL-B Datasheet - production data Cyclic redundancy check (CRC) unit End-to-end Error Correction Code (e2eECC) logic Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC eTQFP64 (10 x 10 x 1.0 mm) eTQFP100 (14 x 14 x 1.0 mm) Body cross triggering unit (BCTU) Triggers ADC conversions from any eMIOS channel Triggers ADC conversions from up to 2 dedicated PIT RTIs QFN48 (7x7 x0.9 mm) 1 event configuration register dedicated to each timer event allows to define the corresponding ADC channel Synchronization with ADC to avoid collision Features 1 enhanced 12-bit SAR analog-to-digital converters AEC-Q100 qualified Up to 27 channels High performance e200z2 single core enhanced diagnosis feature 32-bit Power Architecture technology CPU Communication interfaces Core frequency as high as 80 MHz 6 LINFlexD modules Variable Length Encoding (VLE) 4 deserial serial peripheral interface (DSPI) Floating Point, End-to-End Error Correction modules 1088 KB (1024 KB code flash + 64 KB data 7 MCAN interfaces with advanced shared flash) on-chip flash memory: supports read memory scheme and ISO CAN FD support during program and erase operations, and Dual phase-locked loops with stable clock multiple blocks allowing EEPROM emulation domain for peripherals and FM modulation 96 KB on-chip general-purpose SRAM domain for computational shell Multi-channel direct memory access controller Nexus Class 3 debug and trace interface (eDMA) with 16 channels Boot assist Flash (BAF) supports factory 1 interrupt controller (INTC) programming using a serial bootload through Comprehensive new generation ASIL-B safety the asynchronous CAN or LIN/UART. concept Enhanced modular IO subsystem (eMIOS): up ASIL-B of ISO 26262 to 32 timed I/O channels with 16-bit counter FCCU for collection and reaction to failure resolution notifications Advanced and flexible supply scheme Memory Error Management Unit (MEMU) On-chip voltage regulator for 1.2 V core for collection and reporting of error events logic supply. in memories Junction temperature range -40 C to 150 C December 2020 DS11597 Rev 4 1/115 This is information on a product in full production. www.st.com Table 1. Device summary Part number Package 1 MB 768 kB 512 kB eTQFP64 SPC582B60E1 SPC582B54E1 SPC582B50E1 eTQFP100 SPC582B60E3 SPC582B54E3 SPC582B50E3 QFN48 SPC582B60Q3 SPC582B54Q3 SPC582B50Q3 2/115 DS11597 Rev 4