SPC58EHx, SPC58NHx A scalable approach for high-end body, networking and security platforms for Automotive Data brief Comprehensive new generation ASIL-D safety concept: ASIL-D of ISO 26262 One CPU channel in lockstep eTQFP144 (20x20x1 mm) eLQFP176 (24x24x1 mm) Logic BIST FCCU for collection and reaction to failure notifications FPBGA302 (17x17x1.8 mm) FPBGA386 (19x19x1.8 mm) Memory BIST Cyclic redundancy check (CRC) unit Features Memory Error Management Unit (MEMU) for collection and reporting of error events AEC-Q100 qualified in memories High performance e200z4 triple core: Crossbar switch architecture for concurrent 32-bit Power Architecture technology CPU access to peripherals, Flash, or RAM from Core frequency as high as 200 MHz multiple bus masters with end-to-end ECC Variable Length Encoding (VLE) Body cross triggering unit (BCTU): Floating Point, End-to-End Error Correction Triggers ADC conversions from any eMIOS 10496 KB (10240 KB code Flash + 256 KB channel data Flash) on-chip Flash memory: Triggers ADC conversions from up to 2 Supports read during program and erase dedicated PIT RTIs operations, and multiple blocks allowing Enhanced modular IO subsystem (eMIOS): EEPROM emulation up to 96 timed IO channels with 16-bit Supports read while read between the two counter resolution code Flash partitions Enhanced analog-to-digital converter system Hardware support for Flash context with: switching (for FOTA with multi software 4 independent fast 12-bit SAR analog versions) converters 1088 KB on-chip general-purpose SRAM (in One supervisor 12-bit SAR analog addition to 192 KB core local data RAM): converter 64 KB in CPU 0, 64 KB in CPU 1 and One standby 10-bit SAR analog converter 64 KB in CPU 2 100 ADC channels 224 KB HSM dedicated Flash memory (192 KB Communication interfaces: code + 32 KB data) 24 LINFlexD modules Multi-channel direct memory access controller 10 deserial serial peripheral interface (eDMA): (DSPI) modules One eDMA with 64 channels 1 deserial serial peripheral interface One eDMA with 16 channels (DSPI LP) module available in low power One interrupt controller (INTC) mode July 2020 DB3758 Rev 2 1/7 For further information contact your local STMicroelectronics sales office. www.st.comSPC58EHx, SPC58NHx 16 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support Dual-channel FlexRay controller One SD/SDIO/eMMC module One OctalSPI module with double Chip Select Two independent Ethernet controllers, one 10/100Mbps and the other one 10/100Mbps or 1Gbps, compliant IEEE 802.3-2008 and OPEN RGMII EPL v2.3 2 Four I C modules Two PSI5 modules Low power capabilities: Versatile low power modes Ultra low power standby with RTC Smart Wake-up Unit for contact monitoring Fast wakeup schemes Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART Low power supply options: Single internal linear regulator with external ballast External low voltage supply (1.2 V) Temperature range: -40 C to 105 C -40 C to 125 C Table 1. Device summary Part number Package 6 MB 8 MB 10 MB Dual core Triple core Dual core Triple core Dual core Triple core eTQFP144 SPC58EH84E5 SPC58NH84E5 SPC58EH90E5 SPC58NH90E5 SPC58EH92E5 SPC58NH92E5 eLQFP176 SPC58EH84E7 SPC58NH84E7 SPC58EH90E7 SPC58NH90E7 SPC58EH92E7 SPC58NH92E7 FPBGA302 SPC58EH84C3 SPC58NH84C3 SPC58EH90C3 SPC58NH90C3 SPC58EH92C3 SPC58NH92C3 FPBGA386 SPC58EH84C5 SPC58NH84C5 SPC58EH90C5 SPC58NH90C5 SPC58EH92C5 SPC58NH92C5 2/7 DB3758 Rev 2