ST10F269Z2Q3

ST10F269Z1-ST10F269Z2 16-bit MCU with MAC unit, 128- to 256-Kbyte Flash memory and 12-Kbyte RAM Datasheet - production data Features High performance 32 or 40 MHZ CPU with DSP function 16-bit CPU With 4-stage pipeline TQFP144 (20 x 20 x 1.40 mm) (Thin Quad Flat Pack) 50 ns (or 62.5 ns) instruction cycle time at Timers: two multi-functional general purpose 40 MHz (or 32 MHz) max CPU Clock timer units with 5 timers Multiply/accumulate unit (Mac) 16 X 16-bit Two 16-channel capture / compare units multiplication, 40-bit accumulator A/D converter Repeat unit 16-channel 10-bit Enhanced boolean bit manipulation 4.85 s conversion time at 40 MHz CPU facilities clock (6.06 s at 32 MHz) Additional instructions to support HLL and operating systems 4-channel PWM unit Single-cycle context switching support Serial channels Memory organization Synchronous / asynchronous serial channel 128 - or 256-Kbyte on-chip Flash memory single voltage with erase/program High-speed synchronous channel controller Two CAN 2.0B interfaces operating on 1 or 2 Up to 1K erasing/programming cycles CAN buses (30 or 2x15 message objects) Up to 16-Mbyte linear address space for Fail-safe protection code and data (5 Mbytes with CAN) Programmable watchdog timer 2-Kbyte on-chip internal RAM (IRAM) Oscillator watchdog 10- Kbyte on-chip extension RAM (XRAM) On-chip bootstrap loader Fast and flexible bus Clock generation Programmable external bus characteristics On-chip PLL for different address ranges Direct or prescaled clock input 8-bit or 16-bit external data bus Real time clock Multiplexed or demultiplexed external address / data buses Up to 111 general purpose I/O lines Five programmable chip-select signals Individually programmable as Input, output Hold-acknowledge bus arbitration support or special function Programmable threshold (hysteresis) Interrupt 8-channel peripheral event controller for Idle and Power-down modes single cycle interrupt driven data transfer Single voltage supply: 5V 10% (embedded 16-priority-level interrupt system with 56 regulator for 2.7 or 3.3 V core supply). sources, sampling rate down to 25 ns at Temperature ranges: -40 +125C/ -40 to 85C 40 MHz (31.25 ns at 32 MHz) 144-pin TQFP package September 2017 DocID13266 Rev 2 1/206 This is information on a product in full production. www.st.comContents ST10F269Z1-ST10F269Z2 Contents 1 Introduction . 12 2 Pin Data 14 3 Functional Description 20 4 Memory Organization . 21 5 Internal Flash Memory 24 5.1 Overview . 24 5.2 Operational Overview 24 5.2.1 Read Mode 24 5.2.2 Instructions and Commands . 25 5.2.3 Status Register . 25 5.2.4 Erase Operation . 26 5.2.5 Erase Suspend . 26 5.2.6 In-System Programming 26 5.2.7 Read/Write Protection 26 5.2.8 Power Supply, Reset . 26 5.3 Architectural Description . 27 5.3.1 Read Mode 27 5.3.2 Command Mode 27 5.3.3 Ready/Busy Signal 27 5.3.4 Flash Status Register . 28 5.3.5 Flash Protection Register . 29 5.3.6 Instructions Description . 29 5.3.7 Reset Processing and Initial State . 34 5.4 Flash Memory Configuration 34 5.5 Application Examples 34 5.5.1 Handling of Flash Addresses . 34 5.5.2 Basic Flash Access Control 35 5.5.3 Programming Examples 36 5.6 Bootstrap Loader . 39 5.6.1 Entering the Bootstrap Loader 39 2/206 DocID13266 Rev 2