ST10F272M 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM Datasheet production data Features 16-bit CPU with DSP functions 50ns instruction cycle time at 40 MHz max CPU clock Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator PP * 3*5, Enhanced boolean bit manipulations Single-cycle context switching support On-chip memories 24-channel A/D converter 256 Kbyte Flash memory (32-bit fetch) 16-channel 10-bit, accuracy 2 LSB Single voltage Flash memories with 8-channel 10-bit, accuracy 5 LSB erase/program controller and 100 K 4.85 s minimum conversion time erasing/programming cycles. Up to 16 Mbyte linear address space for 4-channel PWM unit + 4-channel XPWM 2 code and data (5 Mbytes with CAN or I C) 2 CAN 2.0B interfaces operating on 1 or 2 CAN 2 Kbyte internal RAM (IRAM) busses (64 or 2x32 message, C-CAN version) 18 Kbyte extension RAM (XRAM) Fail-safe protection Programmable external bus configuration & Programmable watchdog timer characteristics for different address ranges Oscillator watchdog 5 programmable chip-select signals On-chip bootstrap loader Hold-acknowledge bus arbitration support Clock generation Interrupt On-chip PLL with 4 to 8 MHz oscillator 8-channel peripheral event controller for Direct or prescaled clock input single cycle interrupt driven data transfer Real-time clock and 32 kHz on-chip oscillator 16-priority-level interrupt system with 56 sources, sampling rate down to 25 ns Up to 111 general purpose I/O lines Timers Individually programmable as input, output or special function 2 multi-functional general purpose timer units with 5 timers Programmable threshold (hysteresis) Two 16-channel capture/compare units Idle, power-down and stand-by modes Serial channels Single voltage supply: 5 V 10 % (embedded regulator for 1.8 V core supply) 2 synch./asynch. serial channels 2 high-speed synchronous channels Temperature range: -40 to +125 C 2 One I C standard interface September 2013 Doc ID 12968 Rev 4 1/176 This is information on a product in full production. www.st.com 1 3 /4)Contents ST10F272M Contents 1 Introduction . 11 1.1 Description 11 1.2 Special characteristics . 11 1.2.1 1.2.1 X-peripheral clock gating . 11 1.2.2 1.2.2 Improved supply ring . 11 2 Pin data 13 3 Functional description 20 4 Memory organization . 21 5 Internal Flash memory 25 5.1 Overview . 25 5.2 Functional description . 25 5.2.1 Structure 25 5.2.2 Modules structure . 26 5.2.3 Low power mode 27 5.3 Write operation . 28 5.4 Registers description 28 5.4.1 Flash control register 0 low (FCR0L) . 28 5.4.2 Flash control register 0 high (FCR0H) 29 5.4.3 Flash control register 1 low (FCR1L) . 31 5.4.4 Flash control register 1 high (FCR1H) 31 5.4.5 Flash data register 0 low (FDR0L) . 32 5.4.6 Flash data register 0 high (FDR0H) 32 5.4.7 Flash data register 1 low (FDR1L) . 33 5.4.8 Flash data register 1 high (FDR1H) 33 5.4.9 Flash address register low (FARL) . 33 5.4.10 Flash address register high (FARH) 34 5.4.11 Flash error register (FER) . 34 5.5 Protection strategy 35 5.5.1 Protection registers 35 5.5.2 Flash non-volatile write protection I register (FNVWPIR) . 36 2/176 Doc ID 12968 Rev 4