74HC259D(BJ) Toshiba

74HC259D CMOS Digital Integrated Circuits Silicon Monolithic 74HC259D74HC259D74HC259D74HC259D 1. 1. Functional DescriptionFunctional Description 1. 1. Functional DescriptionFunctional Description 8-Bit Addressable Latch 2. 2. 2. 2. GeneralGeneralGeneralGeneral The 74HC259D is a high speed CMOS ADDRESSABLE LATCH fabricated with silicon gate C2MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The respective bits are controlled by address inputs A, B, and C. When CLEAR input is held high and enable input G is held low, the data is written into the bit selected by address inputs, the other bit hold their previous conditions. When both CLEAR and G held high, writing of all bits is inhibited regardless of adress inputs, and their previous condition are held. When CLEAR is held low and G is held high, all bits are resent to low regardless of the other inputs. When both of CLEAR and G held low, all bits which isn t selected by adress inputs are resent to low. All inputs are equipped with protection circuits against static discharge or transient excess voltage. 3. 3. FeaturesFeatures 3. 3. FeaturesFeatures (1) High speed: t = 15 ns (typ.) at V = 5 V pd CC (2) Low power dissipation: I = 4.0 A (max) at T = 25 CC a (3) Balanced propagation delays: t t PLH PHL (4) Wide operating voltage range: V = 2.0 to 6.0 V CC(opr) 4. 4. 4. 4. PackagingPackagingPackagingPackaging SOIC16 Start of commercial production 2016-05 2016 Toshiba Corporation 2016-08-04 1 Rev.3.074HC259D 5. 5. 5. 5. Pin AssignmentPin AssignmentPin AssignmentPin Assignment 6. 6. MarkingMarking 6. 6. MarkingMarking 7. 7. 7. 7. IEC Logic SymbolIEC Logic SymbolIEC Logic SymbolIEC Logic Symbol 2016 Toshiba Corporation 2016-08-04 2 Rev.3.0