TC74AC74F(EL,F) Toshiba

TC74AC74P/F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC74P, TC74AC74F, TC74AC74FT Dual D-Type Flip Flop with Preset and Clear TC74AC74P The TC74AC74 is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate and double-layer metal wiring 2 C MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input to an L level. TC74AC74F All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features High speed: f = 200 MHz (typ.) at V = 5 V max CC Low power dissipation: I = 4 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Symmetrical output impedance: I = I = 24 mA (min) OH OL TC74AC74FT Capability of driving 50 transmission lines. Balanced propagation delays: t t pLH pHL Wide operating voltage range: V = 2 V to 5.5 V CC (opr) Pin and function compatible with 74F74 Weight DIP14-P-300-2.54 : 0.96 g (typ.) SOP14-P-300-1.27A : 0.18 g (typ.) TSSOP14-P-0044-0.65A : 0.06 g (typ.) Start of commercial production 1986-05 1 2014-03-01 TC74AC74P/F/FT Pin Assignment IEC Logic Symbol (4) S 1PR (5) 1Q 1CLR 1 14 V (3) CC 1CK C1 (2) 1D 1D (6) 1D 2 13 2CLR 1Q (1) 1CLR CK D R (10) Q Q 1CK 12 2D 2PR 3 (9) 2Q (11) 2CK 1PR 4 11 2CK (12) 2D (8) 2Q (13) 2CLR 1Q 5 10 2 PR CK D 1Q 6 9 2Q Q Q GND 7 8 2Q (top view) Truth Table Inputs Outputs Function CLR PR D CK Q Q L H X X L H Clear H L X X H L Preset L L X X H H H H L L H H H H H L H H X Q Q No Change n n X: Dont care System Diagram 1/13 CLR 4/10 PR 6/8 Q 2/12 D 5/9 Q 3/11 CK 2 2014-03-01