TC74HC107AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC107AP,TC74HC107AF,TC74HC107AFN Dual J-K Flip Flop with Clear Note: xxxFN (JEDEC SOP) is not available in Japan. The TC74HC107A is a high speed CMOS DUAL J-K FLIP 2 TC74HC107AP FLOP fabricated with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. In accordance with the logic levels applied to the J and K inputs, the outputs change state on the negative going transition of the clock pulse. CLR is independent of the clock and is accomplished by a low logic level on the input. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74HC107AF Features High speed: f = 75 MHz (typ.) at V = 5 V max CC Low power dissipation: I = 2 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Output drive capability: 10 LSTTL loads Symmetrical output impedance: I = I = 4 mA (min) OH OL TC74HC107AFN Balanced propagation delays: t t pLH pHL Wide operating voltage range: V (opr) = 2~6 V CC Pin and function compatible with 74LS107 Pin Assignment Weight DIP14-P-300-2.54 : 0.96 g (typ.) SOP14-P-300-1.27A : 0.18 g (typ.) SOL14-P-150-1.27 : 0.12 g (typ.) IEC Logic Symbol 1 2007-10-01 TC74HC107AP/AF/AFN Truth Table Inputs Outputs Function CLR J K CK Q Q L X X X L H Clear H L L Q Q No Change n n H L H L H H H L H L H H H Q Q Toggle n n H X X Q Q No Change n n X: Dont care System Diagram Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply voltage range V 0.5~7 V CC DC input voltage V 0.5~V + 0.5 V IN CC DC output voltage V 0.5~V + 0.5 V OUT CC Input diode current I 20 mA IK Output diode current I 20 mA OK DC output current I 25 mA OUT DC V /ground current I 50 mA CC CC Power dissipation P 500 (DIP) (Note 2)/180 (SOP) mW D Storage temperature T 65~150 C stg Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (Handling Precautions/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = 40C~65C. From Ta = 65C to 85C a derating factor of 10 mW/C shall be applied until 300 mW. 2 2007-10-01